On the jitter requirements of the sampling clock for analog-to-digital converters
IEEE Transactions on Circuits and Systems I: Fundamental Theory and Applications - Tập 49 Số 9 - Trang 1354-1360 - 2002
Tóm tắt
In this work, the effect of sampling clock jitter on the SNR of an analog-to-digital (AD) conversion is investigated from a practical perspective. Aperture jitter analyses have been dealing up to now with white spectrum jitter. This assumption does not hold for the output of phase-locked loops (PLL)-like frequency synthesizers, where the spectrum is shaped by the loop transfer function. Based on a linear approximation, a powerful expression for the SNR is derived, applicable to a jitter process with a generic autocorrelation function and generic input signal. A lot of different definitions of jitter are available in the literature; this work addresses also the problem of identifying correctly among them the "effective" jitter for a given SNR. This can be profitably used in the specification as well as verification of the jitter requirements of a frequency synthesizer used as sampling clock generator in the AD converter systems. The results have been checked through numerical simulation.
Từ khóa
#Jitter #Sampling methods #Clocks #Analog-digital conversion #Frequency synthesizers #Apertures #Phase locked loops #Transfer functions #Linear approximation #AutocorrelationTài liệu tham khảo
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