On the impact of mode transition on phased transactional memory performance

Journal of Parallel and Distributed Computing - Tập 173 - Trang 126-139 - 2023
Catalina Munoz Morales1, Bruno Honorio1, Joao P.L. de Carvalho2, Alexandro Baldassin3, Guido Araujo1
1University of Campinas (UNICAMP), Institute of Computing, Av. Albert Einstein, 1251 Cidade Universitária, Campinas, 13083-852, Sao Paulo, Brazil
2University of Alberta, Department of Computing Science, 2-32 Athabasca Hall, Edmonton, T6G 2E8, Alberta, Canada
3Univ. Estadual Paulista (UNESP), DEMAC, Avenida 24 A, 1515, Rio Claro, 13506-900, Sao Paulo, Brazil

Tài liệu tham khảo

Alistarh, 2018, Inherent limitations of hybrid transactional memory ARM Brandes, 2001, A faster algorithm for betweenness centrality, J. Math. Sociol., 25, 163, 10.1080/0022250X.2001.9990249 Calciu, 2014, Invyswell: a hybrid transactional memory for Haswell's restricted transactional memory, 187 Carvalho, 2017, Revisiting phased transactional memory Carvalho, 2019, The case for phase-based transactional memory, IEEE Trans. Parallel Distrib. Syst., 30, 459, 10.1109/TPDS.2018.2861712 Carvalho, 2020, Improving transactional code generation via variable annotation and barrier elision, 1008 Cascaval, 2008, Software transactional memory: why is it only a research toy?, Commun. ACM, 51, 40, 10.1145/1400214.1400228 Chakrabarti, 2004 Dalessandro, 2010, NOrec: streamlining STM by abolishing ownership records, 67 Dalessandro, 2011, Hybrid NOrec: a case study in the effectiveness of best effort hardware transactional memory, Comput. Archit. News, 39, 39, 10.1145/1961295.1950373 Damron, 2006 Damron, 2006, Hybrid transactional memory, Oper. Syst. Rev., 40, 336, 10.1145/1168917.1168900 Didona, 2016, ProteusTM: abstraction meets performance in transactional memory, 757 Dragojevic, 2009, Optimizing transactions for captured memory, 214 Dragojevic, 2011, Why STM can be more than a research toy, Commun. ACM, 54, 70, 10.1145/1924421.1924440 Felber, 2010, Time-based software transactional memory, IEEE Trans. Parallel Distrib. Syst., 21, 1793, 10.1109/TPDS.2010.49 Filipe, 2019, Stretching the capacity of hardware transactional memory in IBM power architectures, 107 GCC Gray, 1981, The transaction concept: virtues and limitations, 144 Gray, 1993 Harris, 2010 Hasenplaugh, 2015, Quantifying the capacity limitations of hardware transactional memory, 1 Herlihy, 1993, Transactional memory: architectural support for lock-free data structures, Comput. Archit. News, 21, 289, 10.1145/173682.165164 Intel Le, 2015, Transactional memory support in the IBM power8 processor, IBM J. Res. Dev., 59, 8:1, 10.1147/JRD.2014.2380199 Lev, 2007, PhTM: phased transactional memory Matveev, 2013, Reduced hardware transactions: a new approach to hybrid transactional memory, 11 Matveev, 2015, Reduced hardware NOrec: a safe and scalable hybrid transactional memory, 59 Minh, 2008, Stamp: Stanford transactional applications for multi-processing, 35 Morales, 2021, Improving phased transactional memory via commit throughput and capacity estimation, 44 Morales, 2021, Accelerating graph applications using phased transactional memory, 421 Nakaike, 2015, Quantitative comparison of hardware transactional memory for Blue Gene/Q, zEnterprise EC12, Intel Core, and POWER8, 144 Nguyen, 2013 Wang, 2012 Whang, 2015, Scalable data-driven pagerank: algorithms, system issues, and lessons learned, 438 Yoo, 2008, Kicking the tires of software transactional memory: why the going gets tough, 265 Zeng, 2021, Investigating the semantics of futures in transactional memory systems, 16