Novel silicon-controlled rectifier (SCR) for digital and high-voltage ESD power supply clamp

Weiss G H, Young D E. Transient-induced latchup testing of CMOS integrated circuits. In: Proceedings of Electrical Overstress/Electrostatic Discharge Symposium, Phoenix, 1995. 194–198 Hsu S F, Ker M D. Dependence of device structures on latchup immunity in a high-voltage 40-V CMOS process with drain-extended MOSFETs. IEEE Trans Electron Dev, 2007, 54: 840–851 Chen W Y, Ker M D, Jou Y N, et al. Source-side engineering to increase holding voltage of LDMOS in a 0.5-m 16-V BCD technology to avoid latch-up failure. In: Proceedings of 16th IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits, Suzhou, 2009. 41–44 Ker M D, Hsu K C. Overview of on-chip electrostatic discharge protection design with SCR-based devices in CMOS integrated circuits. IEEE Trans Device Mater Reliab, 2005, 5: 235–249 Ker M D. ESD protection for CMOS ASIC in noisy environments with high-current low-voltage triggering SCR devices. In: Proceedings of 10th Annual IEEE International ASIC Conference and Exhibit, Portland, 1997. 283–286 Lai C H, Liu M H, Su S, et al. A novel gate-coupled SCR ESD protection structure with high latchup immunity for high-speed I/O pad. IEEE Electron Device Lett, 2004, 25: 328–330 Ker M D, Hsu K C. Substrate-triggered SCR device for on-chip ESD protection in fully silicided sub-0.25-μm CMOS process. IEEE Trans Electron Dev, 2003, 50: 397–405 Mergens M P J, Russ C C, Verhage K G, et al. High holding current SCRs (HHI-SCR) for ESD protection and latch-up immune IC operation. In: Proceedings of Electrical Overstress/Electrostatic Discharge Symposium, Charlotte, 2002. 10–17 Bart S, Ilse B, Olivier M, et al. On-chip ESD protection with improved high holding voltage SCR (HHISCR) achieving IEC 8 kV contact system level. In: Proceedings of Electrical Overstress/Electrostatic Discharge Symposium (EOS/ESD), Reno, 2010. 1–10 Ker M D, Chang C H. Stacked-NMOS triggered silicon-controlled rectifier for ESD protection in high/low-voltagetolerant I/O interface. IEEE Electron Device Lett, 2002, 23: 363–365 Quittard O, Mrcarica Z, Blanc F, et al. ESD protection for high-voltage CMOS technologies. In: Proceedings of Electrical Overstress/Electrostatic Discharge Symposium, Tucson, 2006. 77–86 Liu Z W, Liou J J, Vinson J. Novel silicon-controlled rectifier (SCR) for high-voltage electrostatic discharge (ESD) applications. IEEE Electron Device Lett, 2008, 29: 753–755 Liu Z W, Liou J J, Dong S, et al. Silicon-controlled rectifier stacking structure for high-voltage ESD protection applications. IEEE Electron Device Lett, 2010, 31: 845–847 Dong S R, Jin H, Miao M. Novel capacitance coupling complementary dual-direction SCR for high-voltage ESD. IEEE Electron Device Lett, 2012, 33: 640–642 Huang C Y, Chiu F C, Chen Q K, et al. An SCR-incorporated BJT device for robust ESD protection with high latchup immunity in high-voltage technology. IEEE Trans Device Mater Reliab, 2012, 12: 113–123 Zhang P, Wang Y, Jia S, et al. SCR device with high holding current for on-chip ESD protection. In: Proceedings of IEEE Electron Devices and Solid-State Circuits Conference, Tianjin, 2011. 1–2 Chatterjee A, Polgreen T. A low-voltage triggering SCR for on-chip ESD protection at output and input pads. IEEE Electron Device Lett, 1991, 12: 21–22 Keppens B, Wybo G, Vermont G, et al. Concept for body coupling in SOI MOS transistors to improve multi-finger triggering. In: Proceedings of Electrical Overstress/Electrostatic Discharge Symposium, Tucson, 2006. 172–178