Multidimensional fourier transforms by systolic architectures

T.D. Roziner1
1Coll. of Eng., Boston Univ., MA, USA

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Tài liệu tham khảo

R. Storn, “A novel radix-2 pipeline architecture for the computation of the DFT,”ISKAS'88, 1988, pp. 2685–2688.

S. Winograd, “On computing the discrete Fourier transform,”Math. Comput., vol. 32, 1978, pp. 175–199.

Z. Wang, “Fast algorithms for the discreteW transform and fast DFT,”IEEE Trans. Acoustics, Speech, and Signal Processing, vol. ASSP-32, 1984, pp. 803–816.

K.R. Rao, O. Rath, K. Yeng, “Recursive generation of the DIF FFT algorithm by 1-D DFT”,IEEE Trans. ASSP, vol. ASSP-36, 1987, pp. 1534–1536.

K.R. Rao, S. Venkatamaran, V.R. Kanchan, and M. Mohanty, “Discrete transforms via the Walsh-Hadamard transform,”Signal Processing (The Netherlands), vol. 14, 1988, pp. 371–382.

K.R. Rao, P. Yip, “The decimation-in-frequency algorithm for a family of discrete sine and cosine transforms,”Circuits Syst. Signal Processing, vol. 7, 1988, pp. 3–19.

O. Rath, K.R. Rao, K. Yeung, “FFT via the Walsh-Hadamard transform,”20th Asilomar Conf. on Signals, Systems, and Computers. Pacific Grove, CA, 1986, pp. 373–377.

A.M. Despain, “Fourier transform computers using CORDIC iterations,”IEEE Trans. on Comp., vol. C-23, 1974, pp. 993–1001.

J.V. McCanny, J.G. McWhirter, and E.E. Swartzlander Jr., eds.,Systolic Arrays, Englewood Cliffs, NJ: Prentice Hall, 1989.

H.T. Kung, “Let's design algorithms for VLSI systems,” inProc. Caltech Conf. VLSI, 1980, pp. 65–90.

H.T. Kung and C.E. Leiserson, “Systolic arrays for VLSI,” inIntroduction to VLSI systems. (C.A. Mead and L.A. Conway, eds., Reading, MA: Addison-Wesley, 1980.

D.I. Moldovan, “On the analysis and synthesis of VLSI algorithms,”IEEE Trans. on Comp., vol. C-31, 1982, pp. 1121–1126.

D.I. Moldovan, “On the design of algorithms for VLSI systolic arrays,”Proc. IEEE, vol. 71, 1983, pp. 113–120.

D.I. Moldovan and J.A.B. Fortes, “Partitioning and mapping algorithms into fixed size systolic structures,”IEEE Trans. on Comp., vol. C-35, 1986, pp. 1–12.

D. Moldovan, “Towards a computerized optimal design of VLSI systolic arrays”,Design methodologies, Amsterdam, The Netherlands: North Holland, 1986, pp. 215–234.

H.V. Jagadish, S.K. Rao, and T. Kailath, “Architectures for iterative algorithms”,Proc. of IEEE, vol. 75, 1987, pp. 1304–1321.

C.J. Li and B.W. Wah, “The design of optimal systolic arrays”,IEEE Trans. Comp., vol. C-34, 1985, p. 66–77.

I. Gertner and M. Shamash, “VLSI architectures for multidimensional Fourier transform processing”,IEEE Trans. Comp., vol. C-36, 1987, pp. 1265–1274.

M. Marchesi, G. Orlandi, and F. Piazza, “A systolic circuit for Fast Hartley Transform”,ISKAS'88, 1988, pp. 2685–2688.

M.J. Corinthios, “3-D cellular arrays for parallel/cascade image/signal processing”, inSpectral Techniques and Fault Detection, (M. Karpovsky, ed.), New York: Academic Press, 1985.

C. Moraga, “Design of a multiple-valued systolic system for the computation of Chrestenson spectrum”,IEEE Trans. Comp., vol. C-35, 1986, pp. 183–188.

C.D. Thompson, “Fourier Transforms in VLSI”,IEEE Trans. Comp., vol. C-32, 1983, pp. 1047–1057.

C.N. Zhang, D.Y.Y. Yun. “Multidimensional systolic network for DFT”,Proc. 11th Int. Symp. Computer Architecture, Ann Arbor, Mich., 1984, pp. 215–222.

N. Ling and M.A. Bayoumi. “An algorithm transformation technique for multidimensional DSP systolic arrays”,ISCAS'88, pp. 2275–2278.

J.M. Delosme, I.C.F. Ipsen, “Efficient systolic arrays for the solution of Toeplitz systems: An illustration of a methodology for the construction of systolic architectures in VLSI”,Proc. of the 1st Int. Workshop on Systolic Arrays, Oxford, UK, 1986, pp. 37–46.

B.W. Wah, M. Aboelaze, W. Shang: “Systematic designs of buffers in Macropipelines of systolic arrays”,Journal of Parallel and Distributed Computing, vol. 5, 1988, pp. 1–25.

T.D. Roziner, “Systolic macropipelines for multidimensional Fourier transforms”,Parallel Architectures, (N. Rishe, S. Navathe, and D. Tal, eds.),IEEE Computer Society Press, 1991, pp. 216–230.

E.A. Trachtenberg, “Designing standard computer component using spectral techniques”,Proc. of the 1987 IEEE Int. Conf. on Computer design: VLSI in Computers and Processors (ICCD'87), Rye Brook, NY, 1987.

I. Delotto, D. Dotti, “Two-dimensional transform by minicomputers without matrix transposing”,Computer graphics and Image Processing, vol. 4, 1970, pp. 271–278.

R.P. Brent, H.T. Kung, “The area-time complexity of binary multipliers”,Journal of ACM, vol. 28, 1981, pp. 521–534.

F.P. Preparata. “A mesh-connected area-time optimal VLSI multiplier of large integers”,IEEE Trans. Comp., vol. C-32, 1983, pp. 194–198.

R.M. Owens, M.J. Irwin, “Being stingy with multipliers”,IEEE Trans. Comp., vol. C-39, 1990, pp. 809–818.

H.T. Kung and C.E. Leiserson, “Systolic arrays for VLSI”,Introduction to VLSI Systems, Reading, MA: Addison-Wesley, 1980, pp. 260–292.

W.L. Miranker and A. Winkler, “Space-time representation of computational structures”,Computing, vol. 32, 1983, pp. 93–114.

P.R. Capello and K. Steiglitz, “Simplifying VLSI array design with geometric transformations”, inProc. IEEE Int. Conf. Parallel Processing, 1983, pp. 448–457.

J.A.B. Fortes, K.S. Fu, and B.W. Wah, “Systematic approach to the design of algorithmically specified systolic arrays”,Proc. IEEE Int. Conference on ASSP, vol. 1, 1985, pp. 300–303, Tampa, Florida.

J. O'Brien, J. Mather, B. Holland. “A 200 MIPS single-chip 1K FFT processor”, Proc. 1989 IEEE Int. Solid-State Circuits Conf., 1989, pp. 166–167.

S. Magar, S. Shen, G. Luikuo, M. Fleming, R. Agular, “An application specific chipset for 100 MHz data rate”,Proc. of ICASSP, 1988, pp. 1989–1996.

V. Milutinovic, J.A.B. Fortes, L.H. Jamieson, “A multiprocessor architecture for real-time computation of a class of DFT algorithms”,IEEE Trans. ASSP, vol. ASSP-34, 1986, pp. 1301–1309.

R.C. Singleton. “A method for computing the FFT with auxiliary memory and limited high speed storage”,IEEE Trans. Audio and Electroacoustics, vol. AU-15, 1967, pp. 91–98.

N.M. Brenner, “Fast Fourier Transform of externally stored data”,IEEE Trans. Audio and Electroacoustics, vol. AU-17, 1969, pp. 128–132.

H.L. Buijs, “Fast Fourier Transformation of large arrays of data”,Applied Optics, vol. 8, 1969, pp. 211–212.

M.A. Onoe, “A method for computing large-scale 2-D transforms without transposing data matrix”,Proc. IEEE, vol. 63, 1975, pp. 196–197.

R.E. Twogood, M.P. Ekstrom, “An extension of Eklund's matrix transposition algorithm and its application in digital image processing”,IEEE Trans. Comp., vol. C-25, 1976, pp. 950–952.

G.L. Anderson, “A stepwise approach to computing the multidimensional Fourier Transform of large arrays”,IEEE Trans. ASSP, vol. ASSP-28, 1970, pp. 280–284.

D.B. Harris, J.H. McClellan, D. Chan, H.S. Schuessler, “Vector radix FFT”,IEEE Int. Conf. ASSP Proc., 1977, pp. 548–551.

E.A. Hoyer, W.R. Berry, “An algorithm for the 2-D FFT”,IEEE Int. Conf. Proc., 1977, pp. 552–555.

A.L. Gorin, A. Silberger, L. Auslander, “Computing the twodimensional DFT on the ASPEN parallel computer architecture”,Proc. Int. Conference on Computer Architecture, 1988, pp. 921–923.

H.T. Kung, “Why systolic architectures?”,Computer, vol. 15, 1982, pp. 37–46.

M.G. Karpovsky, L.A. Trachtenberg, T.D. Roziner, “Computation of discrete Fourier transforms over finite Abelian groups using pipelined and systolic array architectures”,International Symposium on the Mathematical Theory of Networks and Systems, 1989, Amsterdam, The Netherlands.

T.D. Roziner, M.G. Karpovsky, and L.A. Trachtenberg. “Complexity analysis of generalized FFT in a multiprocessor environment”,12th IMACS Congress on Scientific Computation, 1988, Paris, France.

T.D. Roziner, M.G. Karpovsky, L.A. Trachtenberg, “Fast Fourier transforms over finite groups by multiprocessor systems”,IEEE Trans. ASSP, vol. ASSP-38, 1990, pp. 226–240.

J. Vuillemin, “A combinatorial limit to the computing power of VLSI circuits”,IEEE Trans. Comp., vol. C-32, 1983, pp. 294–200.

Advanced Micro Devices Inc: Bipolar microprocessor and logic interface (AM 2900 Family) Data Book, Sunnyvale, Calif. 1985.