Low-power content addressable memory design using two-layer P-N match-line control and sensing

Integration - Tập 75 - Trang 73-84 - 2020
Sheikh Wasmir Hussain1, Telajala Venkata Mahendra1, Sandeep Mishra2, Anup Dandapat1
1Department of Electronics and Communication Engineering, National Institute of Technology, Meghalaya, Shillong 793003, India
2Department of Electronics and Communication Engineering, Indian Institute of Information Technology Pune, Sudumbare, 412109, India

Tài liệu tham khảo

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