Low-leakage soft error tolerant port-less configuration memory cells for FPGAs
Tài liệu tham khảo
A. Agarwal, C. H. Kim, S. Mukhopadhyay, and K. Roy, Leakage in nano-scale technologies: mechanisms, impact and design considerations, in: Proceeding of the 41st Design Automation Conference, 2004, pp. 6–11.
Lodi, 2006, Low leakage techniques for FPGAs, IEEE Journal of Solid-State Circuits, 41, 1662, 10.1109/JSSC.2006.873217
J. Lamoureux and W. Luk, An overview of low-power techniques for field-programmable gate arrays, in: NASA/ESA Conference on Adaptive Hardware and Systems, 2008, pp. 338–345.
Ebrahimi, 2011, Mitigating soft errors in SRAM-based FPGAs by decoding configuration bits in switch boxes, Elsevier Microelectronics Journal, 42, 12, 10.1016/j.mejo.2010.09.010
Anderson, 2006, Active leakage power optimization for FPGAs, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 25, 423, 10.1109/TCAD.2005.853692
Gh. Asadi and M.B. Tahoori, Soft error rate estimation and mitigation for SRAM based FPGAs, in: Proceeding of the 13th International Symposium on Field-programmable Gate Arrays, 2005, pp. 149–160.
S. Srinivasan, A. Gayasen, N. Vijaykrishnan, M. Kandemir, Y. Xie, and M.J. Irwin, Improving soft-error tolerance of FPGA configuration bits, in: International Conference on Computer Aided Design, 2004, pp. 107–110.
B.S. Gill, G. Papachristou, and F.G. Wolff, A new asymmetric SRAM cell to reduce soft errors and leakage power in FPGA, in: Design Automation & Test in Europe Conference & Exhibition, 2007, pp. 1–6.
Azizi, 2003, Low-leakage asymmetric-cell SRAM, IEEE Transactions on Very Large Scale Integration Systems, 11, 701, 10.1109/TVLSI.2003.816139
S. K. Jain, and P. Agarwal, A low leakage and SNM free SRAM cell design in deep sub micron CMOS technology, in: Proceedings of the 19th International Conference on VLSI Design, 2006, pp. 495–498.
S. Miao, P. Ou, X. Zhou, and L. Wang, Zero-hardened SRAM cells to improve soft error tolerance in FPGA, in: Proceedings of the International Symposium on Intelligent Information Technology Application,2008, pp. 278282.
Azizi Mazreah, 2011, New configuration memory cells for FPGA in nano-scaled CMOS technology, Elsevier Microelectronics Journal, 42, 1187, 10.1016/j.mejo.2011.07.008
Calin, 1996, Upset hardened memory design for submicron CMOS technology, IEEE Transactions on Nuclear Science, 43, 2874, 10.1109/23.556880
Lin, 2011, A 11-transistor nanoscale CMOS memory cell for hardening to soft errors, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 19, 900, 10.1109/TVLSI.2010.2043271
Jahinuzzaman, 2009, A soft error tolerant 10T SRAM bit-cell with differential read capability, IEEE Transactions Nuclear Science, 56, 3768, 10.1109/TNS.2009.2032090
Wieckowski, 2007, Portless SRAM—A high-performance alternative to the 6T methodology, IEEE Journal of Solid-State Circuits, 42, 2600, 10.1109/JSSC.2007.907173
De Beer, 2003, An SRAM array based on a four-transistor CMOS SRAM cell, IEEE Transactions on Circuits and Systems—I: Fundamental Theory and Applications, 50, 1203, 10.1109/TCSI.2003.816316
Predictive Technology Model, 〈http://www.eas.asu.edu/∼ptm/〉 2010.
KleinOsowski, 2006, Modeling single-event upsets in 65-nm silicon-on-insulator semiconductor devices, IEEE Transactions on Nuclear Science, 53, 3321, 10.1109/TNS.2006.884353
Srinivasan, 1994, Accurate, predictive modeling of soft error rate due to cosmic rays and chip alpha radiation, IEEE International Reliability Physics Symposium, 12
Omana, 2007, Latch susceptibility to transient faults and new hardening approach, IEEE Transactions on Computers, 56, 1255, 10.1109/TC.2007.1070
Chandra, 2008, Impact of technology and voltage scaling on the soft error susceptibility in nanoscale CMOS, IEEE International Symposium on Defect and Fault Tolerance of VLSI Systems, 114, 10.1109/DFT.2008.50
Ejlali, 2006, Combined time and information redundancy for SEU-tolerance in energy-efficient real-time systems, IEEE Transactions on Very Large Scale Integration Systems, 14, 323, 10.1109/TVLSI.2006.874355
Azizi Mazreah, 2012, Low-leakage soft error tolerant dual-port SRAM cells for cache memory applications, Elsevier Microelectronics Journal, 10, 1016
Amusan, 2008, Single event upsets in deep-submicrometer technologies due to charge sharing, IEEE Transactions on Device and Materials Reliability., 8, 582, 10.1109/TDMR.2008.2000892
Mukhopadhyay, 2005, Modeling of failure probability and statistical design of SRAM array for yield enhancement in nanoscaled CMOS, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 24, 1859, 10.1109/TCAD.2005.852295
Hazucha, 2000, Impact of CMOS technology scaling on the atmospheric neutron soft error rate, IEEE Transactions on Nuclear Science, 47, 10.1109/23.903813
Nicolaidis, 2005, Design for soft error mitigation, IEEE Transactions on Device and Materials Reliability, 5, 405, 10.1109/TDMR.2005.855790
