Low-Power Digital Signal Processing Using Approximate Adders

Vaibhav Gupta1, Debabrata Mohapatra2, Anand Raghunathan1, Kaushik Roy1
1Dept. of Electr. & Comput. Eng., Purdue Univ., West Lafayette, IN, USA
2Intel Corp., Santa Clara, CA, , USA

Tóm tắt

Từ khóa


Tài liệu tham khảo

1992, Information TechnologyDigital Compression and Coding of Continuous-Tone Still ImagesRequirements and Guidelines

10.1007/978-1-4615-6199-6

10.1109/TCAD.2008.2009135

10.1145/1450095.1450124

10.1109/DATE.2008.4484850

zhu, 2009, An enhanced low-power high-speed adder for error-tolerant application, Proc IEEE Int Symp Integr Circuits, 69

10.1166/jolpe.2011.1157

shin, 2010, Approximate logic synthesis for error tolerant applications, Proc Design Automat Test Eur, 957

phillips, 2006, Estimating adders for a low density parity check decoder, Proc SPIE, 6313, 631302, 10.1117/12.680199

10.1109/TCSI.2009.2027626

10.1109/ATS.2008.75

kelly, 2005, Arithmetic data value speculation, Proc Asia-Pacific Comput Syst Architect Conf, 353, 10.1007/11572961_28

10.1109/MC.2004.1274006

10.1007/978-1-4757-4474-3

10.1109/92.974895

ying, 2012, Nanosim A Next-Generation Solution for SoC Integration Verification

10.1145/313817.313834

10.1109/LPE.2006.4271817

10.1109/T-C.1975.224279

10.1109/TVLSI.2004.826201

10.1109/DATE.2007.364664

10.1145/1594233.1594282

10.1109/VLSID.2011.51

10.1109/SIPS.2009.5336238

10.1109/MC.2008.224

10.1145/1671954.1671959

10.1109/ISLPED.2011.5993675

10.1109/DATE.2010.5457093

lyons, 2009, Full-custom design project for digital VLSI and IC design courses using synopsys generic 90 nm CMOS library, Proc IEEE Int Conf Microelectron Syst Edu, 45

rabaey, 1996, Digital Integrated Circuits A Design Perspective

parhi, 1999, VLSI Digital Signal Processing Systems Design and Implementation

10.1109/30.125072