Lightweight implementation of SILC, CLOC, AES-JAMBU and COLM authenticated ciphers

Bellare, 2000, Authenticated encryption: relations among notions and analysis of the generic composition paradigm, 531 M.J. Dworkin, “Recommendation for block cipher modes of operation: the ccm mode for authentication and confidentiality, NIST special publication 800-38C,” 2004. M.J. Dworkin, “Recommendation for block cipher modes of operation: galois/Counter mode (GCM) and GMAC, NIST special publication 800-38D,” 2007. F. Abed, C. Forler, and S. Lucks, “General overview of the first-round caesar candidates for authenticated encryption,” Cryptology ePrint Archive, Report 2014/792. [Online]. Available:https://eprint.iacr.org/2014/792. “CAESAR: Competition For Authenticated Encryption: Security, Applicability, And Robustness.” [Online]. Available: http://competitions.cr.yp.to/caesar.html. Zhang, 2018, Survey of design and security evaluation of authenticated encryption algorithms in the CAESAR competition, Front. Inf. Technol. Electron. Eng., 19, 1475, 10.1631/FITEE.1800576 “Cryptographic competitions.” [Online]. Available:https://competitions.cr.yp.to/. E. Homsirikamol et al., “CAESAR hardware api.,” IACR Cryptology ePrint Archive, Report 2016/626. [Online]. Available:https://eprint.iacr.org/2016/626.pdf. M. Dworkin, “Recommendation for block cipher modes of operation: methods and techniques,” NIST Special Publication 800-38A, 2001. Halevi, 2004, A parallelizable enciphering mode, 292 Datta, 2017, Understanding RUP integrity of COLM, IACR Trans. Symmetric Cryptol., 217 S. Banik, A. Bogdanov, and F. Regazzoni, “Atomic-AES v 2.0.,” IACR Cryptology ePrint Archive, Report 2016/1005. [Online]. Available: Available:http://eprint.iacr.org/2016/1005. “The VHDL source code.” [Online]. Available:https://github.com/mjsru/AE-Hardware. T. Iwata, K. Minematsu, J. Guo, and E. Kobayashi, “CLOC and SILC,” 2016. [Online]. Available:http://competitions.cr.yp.to/round3/clocsilcv3.pdf. A.E. Mode, “The JAMBU lightweight authentication encryption mode (v2. 1),” 2016. [Online]. Available:http://competitions.cr.yp.to/round3/jambuv21.pdf. E. Andreeva et al., “COLM v1,” CAESAR competition proposal, 2016. [Online]. Available:http://competitions.cr.yp.to/round3/colmv1.pdf. Hatzivasilis, 2018, A review of lightweight block ciphers, J. Cryptogr. Eng., 1 Engels, 2011, The hummingbird-2 lightweight authenticated encryption algorithm, 19 Saarinen, 2013, Related-key attacks against full hummingbird-2, 467 Bilgin, 2013, Fides: lightweight authenticated cipher with side-channel resistance for constrained hardware, 142 Dinur, 2014, Cryptanalysis of fides, 224 Bogdanov, 2013, ALE: aES-based lightweight authenticated encryption, 447 Khovratovich, 2013, The local attack: cryptanalysis of the authenticated encryption scheme ALE, 174 “GMU implementations of authenticated ciphers, george mason university, U.S.A.” [Online]. Available:https://cryptography.gmu.edu/athena/index.php?id=CAESAR. Banik, 2016, Low-area hardware implementations of CLOC, SILC and AES-OTR, 71 Moradi, 2011, Pushing the limits: a very compact and a threshold implementation of aes, 69 Gross, 2017, Ascon hardware implementations and side-channel evaluation, Microprocess. Microsyst., 52, 470, 10.1016/j.micpro.2016.10.006 Diehl, 2017, RTL implementations and fpga benchmarking of selected CAESAR round two authenticated ciphers, Microprocess. Microsyst., 52, 202, 10.1016/j.micpro.2017.06.003 Deshpande, 2017, Analysis and inner-round pipelined implementation of selected parallelizable caesar competition candidates, 274 S. Kumar, J. Haj-Yihia, M. Khairallah, M.A. Elmohr, and A. Chattopadhyay, “A comprehensive performance analysis of hardware implementations of CAESAR candidates.,” IACR Cryptology ePrint Archive, Report 2017/1261. [Online]. Available:https://eprint.iacr.org/2017/1261. “Cryptographic engineering research group (CERG) at GMU. development package for hardware implementations compliant with the CAESAR hardware api v1 (2016).” [Online]. Available:https://cryptography.gmu.edu/athena/index.php?id=CAESAR. “Cryptographic engineering research group (CERG) at GMU. development package for hardware implementations compliant with the caesar hardware api v2. (2017).” [Online]. Available:https://cryptography.gmu.edu/athena/index.php?id=CAESAR. Banik, 2016, Atomic-AES: a compact implementation of the AES encryption/decryption core, 173 Feldhofer, 2005, AES implementation on a grain of sand, IEE Proc.-Inf. Secur., 152, 13, 10.1049/ip-ifs:20055006 Mathew, 2015, 340mV–1.1V, 289Gbps/W, 2090-gate nanoAES hardware accelerator with area-optimized encrypt/decrypt Gf (2 4) 2 polynomials in 22nm tri-gate CMOS, IEEE J. Solid-State Circuits, 50, 1048, 10.1109/JSSC.2014.2384039 Chu, 2012, Low area memory-free FPGA implementation of the aes algorithm, 623 G.T. Sasdrich P, Pushing the limits: ultra-lightweight AES on reconfigurable hardware. in: workshop on trustworthy manufacturing and utilization of secure devices, 2015. Khairallah, 2017, Looting the LUTs: FPGA optimization of AES and AES-like ciphers for authenticated encryption, 282 Farahmand, 2017, Minerva: automated hardware optimization tool, 1 NANGATE: the nangate 45nm Open cell library.[Online]. Available: http://www.nangate.com.