Injection of functional faults in VHDL-description of digital devices
Tóm tắt
A technique of describing functional faults in digital devices in the VHDL language is described. It is shown that injection of faults into models by means of a modification of the initial language constructions does not provide an adequate representation of physical defects. It is proposed that models of functional faults that have been obtained following technological synthesis of designed devices should be incorporated into the VHDL description.
Tài liệu tham khảo
Bibilo, P.N., Sintez logicheskikh skhem s ispol’zovaniem yazyka VHDL (Synthesis of Logic Circuits Using the VHDL Language), SOLON-R, 2002.
Hwang, E.O., Digital Logic and Microprocessor Design with VHDL, Brooks/Cole, 2005.
Lala, P.K., Digital Circuits Testing and Testability, Academic Press, 1997.
Stroud, C. E., A Designer’s Guide to Built-in Self-Test, Kluwer Academic Publishers, 2002.
Zolotorevich, L.A., Simulation of VLSI Faults at Behavioral Level in VHDL, Informatika, 2005, no. 3, pp. 135–144.
Zolotarevich, L.A., Simulation of Faults in VLSI Structures in VHDL, Informatika, 2005, no. 1, pp. 89–94.
Youngmin, H. and Szygenda, S.A., Design Error Simulation Based on Error Modeling and Sampling Techniques, Math. Computers in Simulation, 1993, vol. 46, no. 11, pp. 35–46.
Jenn, E., Arhat, J., Rimen, M., Ohlsson, J., and Karlsson, J., Fault Injection into VHDL Models: The MEFISTO Tool, Proc. 24th Intern. Symp. Fault Tolerant Computing, 1994, pp. 66–75.
Sieh, V., Tschache, O., and Balbach, F., VERIFY: Evaluation of Reliability Using VHDL-Models with Embedded Fault Descriptions, Proc. 27th Inter. Symp. Fault-Tolerant Computing, 1997, pp. 32–36.
Xilinx Integrated Software Environment 8.2i, Xilinx, Inc., http://www.xilinx.com, 2006.
Rincon, A.M., Cherichetti, Monzel, J.A., Stauffer, D.R., and Trick M.T., Core Design and System-on-a-chip Integration, IEEE Design Test Computers, 1997, no. 14, pp. 26–35.
Hunt, M. and Rowson J.A., Blocking in a System on a Chip, IEEE Spectrum, 1996, no. 11, pp. 35–41.
Bergeron, J., Writing Testbenches. Functional Verification of HDL Models, Kluwer Academic Pablishers, 2000.
Yarmolik, V.N., Kontrol’i diagnostika tsifrovykh uzlov EVM (Control and Diagnostics of Digital Components in Computers), Minsk: Nauka i Tekhnika, 1988.