Implementation of a spike-based perceptron learning rule using TiO2−x memristors
Tóm tắt
Từ khóa
Tài liệu tham khảo
Benjamin, 2014, Neurogrid: a mixed-analog-digital multichip system for large-scale neural simulations, Proc. IEEE, 102, 699, 10.1109/jproc.2014.2313565
Bi, 1998, Synaptic modifications in cultured hippocampal neurons: dependence on spike timing, synaptic strength, and postsynaptic cell type, J. Neurosci., 18, 10464, 10.1523/JNEUROSCI.18-24-10464.1998
Binzegger, 2004, A quantitative map of the circuit of cat primary visual cortex, J. Neurosci., 24, 8441, 10.1523/JNEUROSCI.1400-04.2004
Brader, 2007, Learning real world stimuli in a neural network with spike-driven synaptic dynamics, Neural Comput., 19, 2881, 10.1162/neco.2007.19.11.2881
Chicca, 2014, Neuromorphic electronic circuits for building autonomous cognitive systems, Proc. IEEE, 102, 1367, 10.1109/JPROC.2014.2313954
Chua, 1971, Memristor-the missing circuit element, Circ. Theory IEEE Trans., 18, 507, 10.1109/TCT.1971.1083337
Clopath, 2010, Voltage and spike timing interact in stdp – a unified model, Front. Synaptic Neurosci., 2, 10.3389/fnsyn.2010.00025
Delbruck, 2006, Fully programmable bias current generator with 24 bit resolution per bias, Circuits and Systems, 2006. ISCAS 2006. Proceedings 2006. IEEE International Symposium, 4
Du, 2014, Novel implementation of memristive systems for data encryption and obfuscation, J. Appl. Phys., 115, 124501, 10.1063/1.4869262
FACETS., 2005–2009, Fast Analog omputing with Emergent Transient States in Neural Architectures (FACETS)
Fusi, 2000, Spike–driven synaptic plasticity: theory, simulation, VLSI implementation, Neural Comput., 12, 2227, 10.1162/089976600300014917
Graupner, 2012, Calcium-based plasticity model explains sensitivity of synaptic changes to spike pattern, rate, and dendritic location, Proc. Natl. Acad. Sci. U.S.A., 109, 3991, 10.1073/pnas.1109359109
Indiveri, 2010, Spike-based learning with a generalized integrate and fire silicon neuron, International Symposium on Circuits and Systems, (ISCAS), 2010, 1951, 10.1109/ISCAS.2010.5536980
Indiveri, 2013, Integration of nanoscale memristor synapses in neuromorphic computing architectures, Nanotechnology, 24, 384010, 10.1088/0957-4484/24/38/384010
Jo, 2010, Nanoscale memristor device as synapse in neuromorphic systems, Nano Lett., 10, 1297, 10.1021/nl904092h
Lin, 2010, Efficient image encryption using a chaos-based pwl memristor, IETE Tech. Rev., 27, 318, 10.4103/0256-4602.64605
Linn, 2012, Beyond von neumann - logic operations in passive crossbar arrays alongside memory perations, Nanotechnology, 23, 305205, 10.1088/0957-4484/23/30/305205
Lisman, 2010, Questions about stdp as a general model of synaptic plasticity, Front. Synaptic Neurosci., 2, 10.3389/fnsyn.2010.00140
Maass, 2002, Synapses as dynamic memory buffers, Neural Netw., 15, 155, 10.1016/S0893-6080(01)00144-7
Mayr, 2010, Rate and pulse based plasticity governed by local synaptic state variables, Front. Synaptic Neurosci., 2, 10.3389/fnsyn.2010.00033
Mayr, 2012, Waveform driven plasticity in BiFeO3 memristive devices: model and implementation, Advances in Neural Information Processing Systems 25, 1700
Merolla, 2014, A million spiking-neuron integrated circuit with a scalable communication network and interface, Science, 345, 668, 10.1126/science.1254642
Mitra, 2009, Real-time classification of complex patterns using spike-based learning in neuromorphic VLSI, Biomed. Circ. Syst. IEEE Trans., 3, 32, 10.1109/TBCAS.2008.2005781
Moreno, 2010, Reversible resistive switching and multilevel recording in La0.7Sr0.3MnO3 thin films for low cost nonvolatile memories, Nano Lett., 10, 3828, 10.1021/nl1008162
Navaridas, 2013, Spinnaker: fault tolerance in a power-and area-constrained large-scale neuromimetic architecture, Parallel Comput., 39, 693, 10.1016/j.parco.2013.09.001
Ning, 2015, A re-configurable on-line learning spiking neuromorphic processor, Front. Neurosci., 9, 10.3389/fnins.2015.00141
Noack, 2015, Switched-capacitor realization of presynaptic short-term-plasticity and stop-learning synapses in 28 nm CMOS, Front. Neurosci., 9, 10.3389/fnins.2015.00010
Pfister, 2006, Optimal spike-timing dependent plasticity for precise action potential firing in supervised learning, Neural Comput., 18, 1309, 10.1162/neco.2006.18.6.1318
Qiao, 2015, A re-configurable on-line learning spiking neuromorphic processor comprising 256 neurons and 128k synapses, Front. Neurosci., 9, 10.3389/fnins.2015.00141
Schemmel, 2007, Modeling synaptic plasticity within networks of highly accelerated I&F neurons, International Symposium on Circuits and Systems, (ISCAS), 2007, 3367, 10.1109/ISCAS.2007.378289
Schemmel, 2012, Live demonstration: a scaled-down version of the BrainScaleS wafer-scale neuromorphic system, IEEE International Symposium on Circuits and Systems ISCAS 2012, 702, 10.1109/ISCAS.2012.6272131
Senn, 2005, Learning only when necessary: better memories of correlated patterns in networks with bounded synapses, Neural Comput., 17, 2106, 10.1162/0899766054615644
Serb, 2015, Limitations and precision requirements for read-out of passive, linear, selectorless rram arrays, Circuits and Systems (ISCAS), 2015 IEEE International Symposium, 189, 10.1109/ISCAS.2015.7168602
Serrano-Gotarredona, 2013, STDP and STDP variations with memristors for spiking neuromorphic learning systems, Front. Neurosci., 7, 10.3389/fnins.2013.00002
Shuai, 2013, Nonvolatile multilevel resistive switching in Ar+ irradiated BiFeO3 thin films, IEEE Electron Device Lett., 34, 54, 10.1109/LED.2012.2227666
Sjöström, 2001, Rate, timing, and cooperativity jointly determine cortical synaptic plasticity, Neuron, 32, 1149, 10.1016/S0896-6273(01)00542-6
Sjöström, 2008, Dendritic excitability and synaptic plasticity, Physiol. Rev., 88, 769, 10.1152/physrev.00016.2007