High-density via RRAM cell with multi-level setting by current compliance circuits
DISCOVER NANO - 2024
Tóm tắt
In this work, multi-level storage in the via RRAM has been first time reported and demonstrated with the standard FinFET CMOS logic process. Multi-level states in via RRAM are achieved by controlling the current compliance during set operations. The new current compliance setting circuits are proposed to ensure stable resistance control when one considers cells under the process variation effect. The improved stability and tightened distributions on its multi-level states on via RRAM have been successfully demonstrated.
Từ khóa
Tài liệu tham khảo
Okhonin S, et al. A capacitor-less 1T-DRAM cell. IEEE Electron Device Lett. 2002;23(2):85–7.
Chang, L., et al. Stable SRAM cell design for the 32 nm node and beyond. In Digest of Technical Papers. 2005 Symposium on VLSI Technology, 2005. 2005. IEEE.
Bez R, et al. Introduction to flash memory. Proc IEEE. 2003;91(4):489–502.
Theis TN, Wong H-SP. The end of moore’s law: a new beginning for information technology. Comput Sci Eng. 2017;19(2):41–50.
Yu S, Chen P-Y. Emerging memory technologies: recent trends and prospects. IEEE Solid-State Circuits Mag. 2016;8(2):43–56.
Bez R, Pirovano A. Non-volatile memory technologies: emerging concepts and new materials. Mater Sci Semicond Process. 2004;7(4–6):349–55.
Wong H-SP, et al. Metal–oxide RRAM. Proc IEEE. 2012;100(6):1951–70.
Shen Z, et al. Advances of RRAM devices: Resistive switching mechanisms, materials and bionic synaptic application. Nanomaterials. 2020;10(8):1437.
Bai Y, et al. Study of multi-level characteristics for 3D vertical resistive switching memory. Sci Rep. 2014;4(1):1–7.
Hsu, C.-W., et al. Self-rectifying bipolar TaO x/TiO 2 RRAM with superior endurance over 10 12 cycles for 3D high-density storage-class memory. In 2013 Symposium on VLSI Technology. 2013. IEEE.
Lin, C.-J., et al., 3D Stackable Via RRAM Cells by Cu BEOL Process in FinFET CMOS Technologies. In 2020 International Symposium on VLSI Technology, Systems and Applications (VLSI-TSA). 2020. IEEE.
Lee, C., et al. Memory-logic hybrid gate with 3D-stackable complementary latches for FinFET-based neural networks. In 2019 IEEE International Electron Devices Meeting (IEDM). 2019. IEEE.
Lee C, et al. Memory-logic hybrid gate with 3-D stackable complementary latches. IEEE Trans Electron Devices. 2020;67(8):3109–14.
Milo V, et al. Accurate program/verify schemes of resistive switching memory (RRAM) for in-memory neural network circuits. IEEE Trans Electron Devices. 2021;68(8):3832–7.
Chen Y-Z, et al. Multilevel anti-fuse cells by progressive rupturing of the High-$\kappa $ Gate Dielectric in FinFET Technologies. IEEE Electron Device Lett. 2016;37(9):1120–2.
Chien, W., et al. Multi-level operation of fully CMOS compatible WOx resistive random access memory (RRAM). In 2009 IEEE International Memory Workshop. 2009. IEEE.
E. Yalon, et al. Detection of the conductive filament growth direction in resistive memoriesin. In 2014 IEEE DRC.
Gao, B., et al. Oxide-based RRAM: Unified microscopic principle for both unipolar and bipolar switching. In 2011 International Electron Devices Meeting. 2011. IEEE.
Zahoor F, Azni-Zulkifli TZ. FA Khanday, Resistive random access memory (RRAM): an overview of materials, switching mechanism, performance, multilevel cell (MLC) storage, modeling, and applications. Nanoscale Res Lett. 2020;15(1):1–26.
Aggarwal B, Gupta M, Gupta AK. A comparative study of various current mirror configurations: Topologies and characteristics. Microelectron J. 2016;53:134–55.
Azhari SJ, Baghtash HF, Monfaredi K. A novel ultra-high compliance, high output impedance low power very accurate high performance current mirror. Microelectron J. 2011;42(2):432–9.
Zeki, A. and H. Kuntman, Accurate and high output impedance current mirror suitable for CMOS current output stages. Electron Lett, 1997. 33(12).
Serrano T, Linares-Barranco B. The active-input regulated-cascode current mirror. IEEE Trans Circuits Syst I Fund Theory Appl. 1994;41(6):464–7.
Cheng, K.-H., C.-C. Chen, and C.-F. Chung. Accurate current mirror with high output impedance. In ICECS 2001. 8th IEEE International Conference on Electronics, Circuits and Systems (Cat. No. 01EX483). 2001. IEEE.
Vajpayee, P., et al. Low voltage regulated cascode current mirrors suitable for sub-1V operation. In 2010 IEEE Asia Pacific Conference on Circuits and Systems. 2010. IEEE.