High-Speed and Energy-Efficient Carry Skip Adder Operating Under a Wide Range of Supply Voltage Levels

Milad Bahadori1, Mehdi Kamal1, Ali Afzali‐Kusha1, Massoud Pedram2
1School of Electrical and Computer Engineering, University of Tehran, Tehran, Iran
2Department of Electrical Engineering , University of Southern California , Los Angeles, CA, USA

Tóm tắt

Từ khóa


Tài liệu tham khảo

10.1109/TC.1982.1675982

2010, Nangate 45 nm Open Cell Library

10.1109/TVLSI.2009.2022531

10.1109/TVLSI.2009.2026280

ghosh, 2008, Exploring high-speed low-power hybrid arithmetic units at scaled supply and adaptive clock-stretching, Proc Asia South Pacific Design Autom Conf (ASPDAC), 635

10.1145/1283780.1283822

rabaey, 2003, Digital Integrated Circuits A Design Perspective

du, 2012, High performance reliable variable latency carry select addition, Proc Design Autom Test Eur Conf Exhibition (DATE), 1257

su, 2011, Performance optimization using variable-latency design style, IEEE Trans Very Large Scale Integr (VLSI) Syst, 19, 1874, 10.1109/TVLSI.2010.2058874

10.1109/ISQED.2010.5450484

10.1109/JPROC.2009.2035453

10.1109/JPROC.2009.2034764

2011, Synopsys HSPICE

jain, 2012, A 280 mV-to-1.2 V wide-operating-range IA-32 processor in 32 nm CMOS, IEEE Int Solid-State Circuits Conf Dig Tech Papers (ISSCC), 66

zimmermann, 1998, Binary adder architectures for cell-based VLSI and their synthesis

10.1109/ACSSC.2003.1292373

10.1109/TC.1973.5009159

10.1109/ARITH.2003.1207688

10.1109/TEC.1961.5219274

10.1109/DSD.2004.1333335

10.1109/TCSI.2002.807517

10.1109/TVLSI.2005.848819

10.1145/1013235.1013312

10.1109/JSSC.2004.838019

10.1109/ICCD.2003.1240880

10.1109/ICCD.2005.71

10.1109/TVLSI.2010.2101621

10.1109/LPE.2005.195498

he, 2008, A power-delay efficient hybrid carry-lookahead/carry-select based redundant binary to two’s complement converter, IEEE Trans Circuits Syst I Reg Papers, 55, 336, 10.1109/TCSI.2007.913610

10.1109/82.539001

10.1109/JSSC.2008.2010795

10.1109/TVLSI.2005.848806

koren, 2002, Computer Arithmetic Algorithms

10.1109/PGEC.1967.264605

10.1109/ARITH.1989.72814

10.1109/TC.1987.1676855

10.1109/12.277297

10.1109/12.156534

jia, 2003, Static CMOS implementation of logarithmic skip adder, Proc IEEE Conf Electron Devices Solid-State Circuits, 509

10.1109/12.247841