High-Performance Low-Power Carry Speculative Addition With Variable Latency

10.1145/2228360.2228509

du, 2012, High performance reliable variable latency carry select addition, Proc Design Autom Test Eur Conf Exhibition (DATE), 1257

10.1109/ICCD.2011.6081446

10.1109/92.924058

10.1145/1283780.1283822

10.1109/TVLSI.2009.2026280

10.1109/ISED.2011.50

su, 2011, Performance optimization using variable-latency design style, IEEE Trans Very Large Scale Integr (VLSI) Syst, 19, 1874, 10.1109/TVLSI.2010.2058874

10.1109/DATE.2009.5090937

10.1109/ISQED.2010.5450484

shin, 2010, Approximate logic synthesis for error tolerant applications, Proc Design Autom Test Eur Conf Exhibition (DATE), 957

10.1109/TCAD.2012.2217962

zhu, 2009, An enhanced low-power high speed adder for error-tolerant application, Proc Int Symp Intell Control (ISIC), 69

10.1109/ISOCC.2011.6138614

10.1109/SOCDC.2010.5682905

zhu, 2010, Design of low-power high-speed truncation-error-tolerant adder and its application in digital signal processing, IEEE Trans Very Large Scale Integr (VLSI) Syst, 18, 1225, 10.1109/TVLSI.2009.2020591

10.1109/ISLPED.2011.5993675

koren, 2002, Computer Arithmetic Algorithms

10.1145/1403375.1403679

rabaey, 2003, Digital Integrated Circuits A Design Perspective

2013, Laker Custom Design and Layout Tool