Hardware-efficient common-feedback Markov-random-field probabilistic-based noise-tolerant VLSI circuits

Integration - Tập 47 - Trang 431-442 - 2014
I-Chyn Wey1, Ye-Jhih Shen2
1Graduate Institute of Electrical Engineering, Electrical Engineering Department, Green Technology Research Center, and Healthy Aging Research Center, Chang-Gung University, Taiwan
2Graduate Institute of Electrical Engineering, Chang-Gung University, Taiwan

Tài liệu tham khảo

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