Four-input-C-element-based multiple-node-upset-self-recoverable latch designs

Integration - Tập 90 - Trang 11-21 - 2023
Shuo Cai1, Caicai Xie1, Yan Wen1, Weizheng Wang1, Fei Yu1, Lairong Yin2
1School of Computer and Communication Engineering, Changsha University of Science and Technology, Changsha, HN 410114, China
2College of Automotive and Mechanical Engineering, Changsha University of Science and Technology, Changsha, HN 410114, China

Tài liệu tham khảo

Gadlage, 2017, Soft errors induced by high-energy electrons, IEEE Trans. Device Mater. Reliab., 17, 157, 10.1109/TDMR.2016.2634626 Cai, 2019, Single event transient propagation probabilities analysis for nanometer CMOS circuits, J. Electron. Test., 35, 163, 10.1007/s10836-019-05791-2 Yan, 2019, Novel double-node-upset-tolerant memory cell designs through radiation-hardening-by-design and layout, IEEE Trans. Reliab., 68, 354, 10.1109/TR.2018.2876243 Liang, 2016, A methodology for characterization of SET propagation in SRAM-based FPGAs, IEEE Trans. Nucl. Sci., 63, 2985, 10.1109/TNS.2016.2620165 El-Maleh, 2021, Time redundancy and gate sizing soft error-tolerant based adder design, Integration, 78, 49, 10.1016/j.vlsi.2021.01.001 Peng, 2019, Radiation-hardened 14T SRAM bitcell with speed and power optimized for space application, IEEE Trans. Very Large Scale Integr. (VLSI) Syst., 27, 407, 10.1109/TVLSI.2018.2879341 Guo, 2018, Design of area-efficient and highly reliable RHBD 10T memory cell for aerospace applications, IEEE Trans. Very Large Scale Integr. (VLSI) Syst., 26, 991, 10.1109/TVLSI.2017.2788439 Yan, 2020, Novel speed-and-power-optimized SRAM cell designs with enhanced self-recoverability from single- and double-node upsets, IEEE Trans. Circuits Syst. I. Regul. Pap., 67, 4684, 10.1109/TCSI.2020.3018328 Yamada, 2018, Radiation-hardened flip-flops with low-delay overhead using pMOS pass-transistors to suppress SET pulses in a 65-nm FDSOI process, IEEE Trans. Nucl. Sci., 65, 1814, 10.1109/TNS.2018.2826726 Alioto, 2015, Variations in nanometer CMOS flip-flops: Part I-impact of process variations on timing, IEEE Trans. Circuits Syst. I. Regul. Pap., 62, 2035, 10.1109/TCSI.2014.2366811 Y. Li, A. Breitenreiter, M. Andjelkovic, O. Schrape, M. Krstic, Flip-Flop SEUs Mitigation through Partial Hardening of Internal Latch and Adjustment of Clock Duty Cycle, in: Proc. 2018 IEEE 21st International Symposium on Design and Diagnostics of Electronic Circuits & Systems, Vol. 19, No. 5, DDECS, 2011, pp. 900–904. Wang, 2019, A layout-based rad-hard DICE flip-flop design, J. Electron. Test., 35, 111, 10.1007/s10836-019-05773-4 Pudi N S, 2016, Robust soft error tolerant CMOS latch configurations, IEEE Trans. Comput., 65, 2820, 10.1109/TC.2015.2509983 Oma?a, 2010, High-performance robust latches, IEEE Trans. Comput., 59, 1455, 10.1109/TC.2010.24 S. Mitra, M. Zhang, N. Seifert, T. Mak, K.S. Kim, Built-In Soft Error Resilience for Robust System Design, in: Proc. 2007 IEEE International Conference on Integrated Circuit Design and Technology, Vol. 20, No. 1, 2020, pp. 181–190. Favalli, 2004, TMR voting in the presence of crosstalk faults at the voter inputs, IEEE Trans. Reliab., 53, 342, 10.1109/TR.2004.833308 P. Hazucha, et al., Measurements and analysis of SER tolerant latch in a 90 nm dual-Vt CMOS process, in: Proc. Proceedings of the IEEE 2003 Custom Integrated Circuits Conference, 2003, pp. 617–620. M. Fazeli, A. Patooghy, S.G. Miremadi, A. Ejlali, Feedback Redundancy: A Power Efficient SEU-Tolerant Latch Design for Deep Sub-Micron Technologies, in: Proc. 37th Annual IEEE/IFIP International Conference on Dependable Systems and Networks, DSN’07, 2007, pp. 276–285. Nan, 2012, Low cost and highly reliable hardened latch design for nanoscale CMOS technology, Microelectron. Reliab., 52, 1209, 10.1016/j.microrel.2012.01.001 Yan, 2015, A self-recoverable, frequency-aware and costeffective robust latch design for nanoscale CMOS technology, IEICE Trans. Electron., 98, 1171, 10.1587/transele.E98.C.1171 Huang, 2015, A high performance SEU tolerant latch, J. Electron. Test., 31, 349, 10.1007/s10836-015-5533-5 Rajaei, 2014, Single event multiple upset (SEMU) tolerant latch designs in presence of process and temperature variations, J. Circuits Syst. Comput., 24, 7 Jiang, 2018, A novel high-performance low-cost double-upset tolerant latch design, Electronics, 7, 1, 10.3390/electronics7100247 N. Eftaxiopoulos, N. Axelos, G. Zervakis, K. Tsoumanis, K. Pekmestzi, Delta DICE: A Double Node Upset resilient latch, in: Proc. 2015 IEEE 58th International Midwest Symposium on Circuits and Systems, MWSCAS, 2015, pp. 1–4. Katsarou, 2015, Soft error interception latch: Double node charge sharing SNU tolerant design, Electron. Lett., 51, 330, 10.1049/el.2014.4374 Yan, 2021, Design of radiation hardened latch and flip-flop with cost-effectiveness for low-orbit aerospace applications, J. Electron. Test., 37, 489, 10.1007/s10836-021-05962-0 Hui, 2015, Circuit and layout combination technique to enhance multiple nodes upset tolerance in latches, IEICE Electron. Express, 12, 1, 10.1587/elex.12.20150286 Yan, 2017, Double-node-upset-resilient latch design for nanoscale CMOS technology, IEEE Trans. Very Large Scale Integr. (VLSI) Syst., 25, 1978, 10.1109/TVLSI.2017.2655079 N. Eftaxiopoulos, N. Axelos, K. Pekmestzi, DONUT: A Double Node Upset Tolerant Latch, in: Proc. 2015 IEEE Computer Society Annual Symposium on VLSI, Vol. 62, No. 6, 2015, pp. 1710–1715. A. Watkins, S. Tragouodas, A Highly Robust Double Node Upset Tolerant latch, in: Proc. 2016 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, DFT, 2016, pp. 15–20. Li, 2015, Double node upsets hardened latch circuits, J. Electron. Test., 31, 537, 10.1007/s10836-015-5551-3 Li, 2019, High robust and cost effective double node upset tolerant latch design for nanoscale CMOS technology, Microelectron. Reliab., 93, 89, 10.1016/j.microrel.2019.01.005 Yan, 2019, A double-node-upset self-recoverable latch design for high performance and low power application, IEEE Trans. Circuits Syst. II, 66, 287 Sajjade, 2019, Rule-based design for multiple nodes upset tolerant latch architecture, IEEE Trans. Device Mater. Reliab., 19, 680, 10.1109/TDMR.2019.2945917 Liu, 2019, Multiple node upset-tolerant latch design, IEEE Trans. Device Mater. Reliab., 19, 387, 10.1109/TDMR.2019.2912811 Watkins, 2020, Radiation hardened latch designs for double and triple node upsets, IEEE Trans. Emerg. Top. Comput., 8, 616, 10.1109/TETC.2017.2776285 Yan, 2021, Novel low cost, double-and-triple-node-upset-tolerant latch designs for nano-scale CMOS, IEEE Trans. Emerg. Top. Comput., 9, 520, 10.1109/TETC.2018.2871861 Yan, 2020, Quadruple cross-coupled dual-interlocked-storage-cells-based multiple-node-upset-tolerant latch designs, IEEE Trans. Circuits Syst. I. Regul. Pap., 67, 879, 10.1109/TCSI.2019.2959007 Yan, 2020, Information assurance through redundant design: A novel TNU error-resilient latch for harsh radiation environment, IEEE Trans. Comput., 69, 789, 10.1109/TC.2020.2966200 Yan, 2020, Design of a triple-node-upset self-recoverable latch for aerospace applications in Harsh radiation environments, IEEE Trans. Aerosp. Electron. Syst., 56, 1163, 10.1109/TAES.2019.2925448 H. Liang, Z. Wang, Z. Huang, A. Yan, Design of a Radiation Hardened Latch for Low-Power Circuits, in: Proc. 2014 IEEE 23rd Asian Test Symposium, 2014, pp. 19–24. Yan, 2022, Novel quadruple-node-upset-tolerant latch designs with optimized overhead for reliable computing in harsh radiation environments, IEEE Trans. Emerg. Top. Comput., 10, 404, 10.1109/TETC.2020.3025584