Finite state machine synthesis with fault tolerant test function
Tóm tắt
Từ khóa
Tài liệu tham khảo
F.C. Hennie, ?Fault detecting experiments for sequential circuits,? inProceedings 5th Annual Symposium on Switching Theory and Logical Design, pp. 95?110, November 1963.
V.D. Agrawal and K.T. Cheng, ?Finite state machine synthesis with embedded test function,?Journal of Electronic Testing: Theory and Applications, vol. 1, pp. 221?228, 1990.
S.M. Reddy and R. Dandapani, ?Scan design using standard flip-flops,?IEEE Design and Test of Computers, vol. 4, pp. 52?54, February 1987.
S. Devadas and K. Keutzer, ?A unified approach to the synthesis of fully testable sequential machines,?IEEE Trans. Comp.-Aided Design, vol. 10, pp. 39?50, January 1991.
S. Devadas and H.T. Ma, ?Easily testable PLA-based finite state machines,?IEEE Trans. on Comp.-Aided Design, vol. 9, pp. 604?611, June 1990.
V.D. Agrawal and D.D. Johnson, ?Logic modeling of PLA faults,? inProceedings of IEEE Int. Conf. on Computer Design, pp. 86?88, October 1986.
T. Villa and A. Sangiovanni-Vincentelli, ?NOVA: State assignment of finite state machines for optimal two-level logic implementations,? inProc. of the 26th Design Auto. Conf., pp. 327?332, June 1989.
W.T. Cheng and T.J. Chakraborty, ?GENTEST: An automatic test generation system for sequential circuits,?Computer, vol. 22, pp. 43?49, April 1989.
J. Jacob and V.D. Agrawal, ?Functional test generation for sequential circuits,? inProc. of the 5th Int. Conf. on VLSI Design, pp. 17?24, January 1991.
J. Rajski and J. Vasudevamurthy, ?Testability preserving transformations in multi-level logic synthesis,? inProc. Int. Test Conference, pp. 265?273, 1990.