Feedback EDF Scheduling of Real-Time Tasks Exploiting Dynamic Voltage Scaling

Arnold, R., Mueller, F., Whalley, D. B., and Harmon, M. 1994. Bounding worst-case instruction cache performance. In IEEE Real-Time Systems Symposium, pp. 172–181.

Aydin, H., Melhem, R., Mosse, D., and Mejia-Alvarez, P. 2001. Dynamic and agressive scheduling techniques for power-aware real-time systems. In IEEE Real-Time Systems Symposium.

Chandrakasan, A., Sheng, S., and Brodersen, R. W. 1992. Low-power Cmos digital design. In IEEE Journal of Solid-State Circuits, 27: pp. 473–484.

Chetto, H. and Chetto, M. 1989. Some Results of the Earliest Deadline Scheduling Algorithm. IEEE Transactions on Software Engineering 15(10): 1261–1269.

D. Shin, J. K. and Lee, S. 2001. Intra-Task Voltage Scheduling for Low-Energy Hard Real-Time Applications. In IEEE Design and Test of Computers.

Dudani, A., Mueller, F., and Zhu, Y. 2002. Energy-Conserving Feedback EDF Scheduling for Embedded Systems with Real-Time Constraints. In ACM SIGPLAN Joint Conference Languages, Compilers, and Tools for Embedded Systems (LCTES'02) and Software and Compilers for Embedded Systems (SCOPES'02), pp. 213–222.

Ferdinand, C., Martin, F., and Wilhelm, R. 1997. Applying Compiler Techiniques to Cache Behavior Prediction. In ACM SIGPLAN Workshop on Language, Compiler, and Tool Support for Real-Time Systems, pp. 37–46.

Govil, K., Chan, E., and Wasserman, H. 1995. Comparing algorithms for dynamic speed-setting of a low-power CPU. In 1st Int'l Conference on Mobile Computing and Networking.

Gruian, F. 2001. Hard real-time scheduling for low energy using stochastic data and DVS processors. In Proceedings of the International Symposium on Low-Power Electronics and Design ISLPED'01.

Gruian, F. and Kuchcinski. 2001. LEneS: Task scheduling for low-energy systems using variable voltage processors. In Proceedings of ASP-DAC.

Grunwald, D., Levis, P., C. M. III, Neufeld, M., and Farkas, K. 2000. Policies for dynamic clock scheduling. In Symp. on Operating Systems Design and Implementation.

Harmon, M., Baker, T. P., and Whalley, D. B. 1992. A Retargetable Technique for Predicting Execution Time. In IEEE Real-Time Systems Symposium, pp. 68–77.

Healy, C. A., Whalley, D. B., and Harmon, M. G. 1995. Integrating the Timing Analysis of Pipelining and Instruction Caching. In IEEE Real-Time Systems Symposium, pp. 288–297.

Hong, I., Potkonjak, M., and Srivastava, M. 1998a. On-line scheduling of hard real-time tasks on variable voltage processor. In Int'l Conference on Computer-Aided Design.

Hong, I., Qu, G., Potkonjak, M., and Srivastava, M. 1998b. Synthesis techniques for low-power hard real-time systems on variable voltage processors. In 19th Real-Time Systems Symposium.

Ishihara, T. and Yasuura, H. 1998. Voltage scheduling problem for dynamically variable voltage processors. In Proceedings of the 1998 International Symposium on Low Power Electronics and Design, pp. 197–202, ACM Press.

Kang, D., Crago, S., and Suh, J. 2002. A Fast Resource Synthesis Technique for Energy-Efficient Real-time Systems. In IEEE Real-Time Systems Symposium.

Krishna, C. and Lee, Y. 2000. Voltage clock scaling adaptive scheduling techniques for low power in hard real-time systems. In 6th Real-Time Technology and Applications Symposium.

Lee, Y. and Krishna, C. 1999. Voltage clock scaling for low energy consumption in real-time embedded systems. In 6th Int'l Conf. on Real-Time Computing Systems and Applications.

Lee, Y.-H. and Krishna, C. M. 2003. Voltage-Clock Scaling for Low Energy Consumption in Fixed-Priority Real-Time Systems. Real-Time Syst. 24(3): 303–317.

Li, Y.-T. S., Malik, S., and Wolfe, A. 1995. Efficient Microarchitecture Modeling and Path Analysis for Real-Time Software. In IEEE Real-Time Systems Symposium, pp. 298–397.

Li, Y.-T. S., Malik, S., and Wolfe, A. 1996. Cache Modeling for Real-Time Software: Beyond Direct Mapped Instruction Caches. In IEEE Real-Time Systems Symposium, pp. 254–263.

Lim, S.-S., Bae, Y. H., Jang, G. T., Rhee, B.-D., Min, S. L., Park, C. Y., Shin, H., and Kim, C. S. 1994. An Accurate Worst Case Timing Analysis for RISC processors. In IEEE Real-Time Systems Symposium, pp. 97–108.

Liu, C. and Layland, J. 1973. Scheduling Algorithms for Multiprogramming in a Hard-Real-Time Environment. J. of the Association for Computing Machinery 20(1): 46–61.

Liu, Y. and Mok, A. K. 2003. An integrated approach for applying dynamic voltage scaling to hard real-time systems. In Proceedings of the ninth IEEE Real-Time and Embedded Technology and Applications Symposium.

Lorch, J. and Smith, A. J. 2001. Improving dynamic voltage scaling algorithms with PACE. In Proceedings of the ACM SIGMETRICS 2001 Conference.

Lu, C., Stankovic, J., Tao, G., and Son, S. 1999. Design and evaluation of a feedback control EDF scheduling algorithm. In IEEE Real-Time Systems Symposium.

Lu, C., Stankovic, J. A., Tao, G., and Son, S. H. 2002a. Feedback Control Real-Time Scheduling: Framework, Modeling, and Algorithms. Real-Time Syst. 23: 85–126.

Lu, Z., Hein, J., Humphrey, M., Stan, M., Lach, J., and Skadron, K. 2002b. Control-Theoretic Dynamic Frequency and Voltage Scaling for Multimedia Workloads. In Conference on Compilers, Architecture and Synthesis for Embedded Systems, pp. 156–63.

Mächtel, M. and Rzehak, H. 1996. Measuring the Influence if Real-Time Operating Systems on Performance and Determinism. Control Eng. Practice 4(10): 1461–1469.

Minerick, R., Freeh, V. W., and Kogge, P. M. 2002. Dynamic Power Management using Feedback. In Proceedings of Workshop on Compilers and Operating Systems for Low Power.

Mosse, D., Aydin, H., Childers, B., and Melhem, R. 2000. Compiler-assisted dynamic power-aware scheduling for real-time applications. In Workshop on Compilers and Operating Systems for Low Power.

Mueller, F. 2000. Timing Analysis for instruction caches. Real-Time Systems 18(2/3): 209–239.

Park, C. Y. 1993. Predicting program execution times by analyzing static and dynamic program paths. Real-Time Systems 5(1): 31–61.

Pering, T., Burd, T., and Brodersen, R. 1995. The simulation of dynamic voltage scaling algorithms. In Symp. on Low Power Electronics.

Pillai, P. and Shin, K. 2001. Real-time dynamic voltage scaling for low-power embedded operating systems. In Symposium on Operating Systems Principles.

Pouwelse, J., Langendoen, K., and Sips, H. 2000. Dynamic voltage scaling on a low-power microprocessor. Technical report, Delft University of Technology.

Puschner, P. and Koza, C. 1989. Calculating the maximum execution time of real-time programs. Real-Time Systems 1(2): 159–176.

Saewong, S. and Rajkumar, R. 2003. Practical voltage-scaling for fixed-priority RT-systems. In Proceedings of the ninth IEEE Real-Time and Embedded Technology and Applications Symposium.

Shin, Y., Choi, K., and Sakurai, T. 2000. Power optimization of real-time embedded systems on variable speed processors. In Int'l Conf. on Computer-Aided Design.

Wegener, J. and Mueller, F. 2001. A comparison of static analysis and evolutionary testing for the verification of timing constraints. Real-Time Systems 21(3): 241–268.

Weiser, M., Welch, B., Demers, A., and Shenker, S. 1994. Scheduling for reduced cpu energy. In 1st Symp. on Operating Systems Design and Implementation.

Zhang, F. and Chanson, S. T. 2002. Processor voltage scheduling for real-time tasks with non-preemptable sections. In IEEE Real-Time Systems Symposium.

Zhang, N., Burns, A., and Nicholson, M. 1993. Pipelined processors and worst case execution times. Real-Time Systems 5(4): 319–343.

Zhu, Y. and Mueller, F. 2002. Preemption handling and scalability of feedback DVS-EDF. In Workshop on Compilers and Operating Systems for Low Power.

Zhu, Y. and Mueller, F. 2004a. Feedback EDF scheduling exploiting dynamic voltage scaling. In IEEE Real-Time Embedded Technology and Applications Symposium, pp. 84–93.

Zhu, Y. and Mueller, F. 2004b. Feedback EDF Scheduling Exploiting Hardware-Assisted Asynchronous Dynamic Voltage Scaling. Technical Report TR 2004-35, Dept. of Computer Science, North Carolina State University.