Fast and Efficient Signature-Based Sub-Circuit Matching

[1] A.M. Gharehbaghi and M. Fujita, “Efficient signature-based sub-circuit matching,” 2015 IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC), pp.280-285, 2015.

[2] D.A. Basin, “A term equality problem equivalent to graph isomorphism,” Inform. Process. Lett., vol.51, no.2, pp.61-66, 1994.

[3] M. Ohlrich, C. Ebeling, E. Ginting, and L. Sather, “SubGemini: Identifying subcircuits using a fast subgraph isomorphism algorithm,” Proc. 30th International on Design Automation Conference, DAC'93, pp.31-37, 1993.

[4] A. Mishchenko, N. Een, R. Brayton, M. Case, P. Chauhan, and N. Sharma, “A semi-canonical form for sequential AIGs,” Design, Automation & Test in Europe Conference & Exhibition (DATE), pp.797-802, 2013.

[5] H. Katebi and I.L. Markov, “Large-scale Boolean matching,” 2010 Design, Automation & Test in Europe Conference & Exhibition (DATE 2010), pp.771-776, 2010.

[6] R. Brayton and A. Mishchenko, “ABC: An academic industrial-strength verification tool,” Computer Aided Verification, Lecture Notes in Computer Science, vol.6174, pp.24-40, 2010.

[7] P. Subramanyan, N. Tsiskaridze, W. Li, A. Gascon, W.Y. Tan, A. Tiwari, N. Shankar, S.A. Seshia, and S. Malik, “Reverse engineering digital circuits using structural and functional analyses,” IEEE Trans. Emerg. Topics Comput., vol.2, no.1, pp.63-80, 2014.

[8] E. Tomita, A. Tanaka, and H. Takahashi, “The worst-case time complexity for generating all maximal cliques and computational experiments,” Theor. Comput. Sci., vol.363, no.1, pp.28-42, 2006.

[9] http://iwls.org/iwls2005/benchmarks.html

[10] Berkeley Logic Synthesis and Verification, http://www.eecs.berkeley.edu/~alanmi/abc/

[11] http://networkx.github.io