Evaluation of wireless network-on-chip architectures with microchannel-based cooling in 3D multicore chips

Sustainable Computing: Informatics and Systems - Tập 21 - Trang 165-178 - 2019
Md Shahriar Shamim1, Rounak Singh Narde2, Jose-Luis Gonzalez-Hernandez3, Amlan Ganguly4, Jayanti Venkatarman2, Satish G. Kandlikar3
1Intel Corp. Hillsboro, OR 97124, United States
2Department of Electrical Engineering at Rochester Institute of Technology, Rochester, NY 14623, United States
3Department of Mechanical Engineering, Rochester Institute of Technology, Rochester, NY 14623, United States
4Department of Computer Engineering, Rochester Institute of Technology, Rochester, NY 14623, United States

Tài liệu tham khảo

Topol, 2006, Three-dimensional integrated circuits, IBM J. Res. Dev., 50, 491, 10.1147/rd.504.0491 Sabry, 2011, Towards thermally-aware design of 3D MPSoCs with inter-tier cooling, 2011 Des. Autom. Test Eur., 1 Tuckerman, 1981, High-performance heat sinking for VLSI, IEEE Electron. Device Lett., 2, 126, 10.1109/EDL.1981.25367 Kandlikar, 2014, Review and projections of integrated cooling systems for three-dimensional integrated circuits, J. Electron. Packag., 136, 24001, 10.1115/1.4027175 Ndao, 2009, Multi-objective thermal design optimization and comparative analysis of electronics cooling technologies, Int. J. Heat Mass Transf., 52, 4317, 10.1016/j.ijheatmasstransfer.2009.03.069 Liu, 2005, Analysis and optimization of the thermal performance of microchannel heat sinks, Int. J. Numer. Methods Heat Fluid Flow., 15, 7, 10.1108/09615530510571921 2015 Deb, 2010, Enhancing performance of network-on-chip architectures with millimeter-wave wireless interconnects, ASAP 2010 - 21st IEEE Int. Conf. Appl. Syst. Archit. Process, 73 Deb, 2012, Wireless NoC as interconnection backbone for multicore chips: promises and challenges, IEEE J. Emerg. Sel. Top. Circ. Syst., 2, 228, 10.1109/JETCAS.2012.2193835 DiTomaso, 2011, iWISE: inter-router wireless scalable express channels for network-on-chips (NoCs) architecture, 2011 IEEE 19th Annu. Symp. High Perform. Interconnects, 11, 10.1109/HOTI.2011.12 Puttaswamy, 2006, Thermal analysis of a 3D die-stacked high-performance microprocessor, Proc. 16th ACM Gt. Lakes Symp. VLSI - GLSVLSI’ 06, 19, 10.1145/1127908.1127915 Biswal, 2009, Design and optimization of single-phase liquid cooled microchannel heat sink, IEEE Trans. Components Packag. Technol., 32, 876, 10.1109/TCAPT.2009.2025598 Sabry, 2013, GreenCool: an energy-efficient liquid cooling design technique for 3-D MPSoCs via channel width modulation, IEEE Trans. Comput. Des. Integr. Circuits Syst., 32, 524, 10.1109/TCAD.2012.2226032 Sabry, 2011, Energy-efficient multiobjective thermal control for liquid-cooled 3-D stacked architectures, IEEE Trans. Comput. Des. Integr. Circuits Syst., 30, 1883, 10.1109/TCAD.2011.2164540 Shi, 2012, TSV-constrained microchannel infrastructure design for cooling stacked 3D-ICs, Proc. 2012 ACM Int. Symp. Int. Symp. Phys. Des. - ISPD’ 12, 113, 10.1145/2160916.2160941 Karkar, 2013, Hybrid wire-surface wave interconnects for next-generation networks-on-chip, IET Comput. Digit. Tech., 7, 294, 10.1049/iet-cdt.2013.0030 Vijayakumaran, 2014, CDMA enabled wireless network-on-Chip, ACM J. Emerg. Technol. Comput. Syst., 10, 1, 10.1145/2536778 Matsutani, 2014, Low-latency wireless 3D NoCs via randomized shortcut chips, Des. Autom. Test Eur. Conf. Exhib. (DATE), 2014, 1 Ouyang, 2010, Evaluation of using inductive/capacitive-coupling vertical interconnects in 3D network-on-chip, 2010 IEEE/ACM Int. Conf. Comput. Des., 477 More, 2010, Wireless interconnects for inter-tier communication on 3D ICs, 105 Yuan, 2014, An exploration on quantity and layout of wireless nodes for hybrid wireless network-on-chip, 2014 IEEE Intl Conf High Perform. Comput. Commun. 2014 IEEE 6th Intl Symp Cybersp. Saf. Secur. 2014 IEEE 11th Intl Conf Embed. Softw. Syst., 100 Ganguly, 2011, Scalable hybrid wireless network-on-Chip architectures for multicore systems, IEEE Trans. Comput., 60, 1485, 10.1109/TC.2010.176 Lin, 2007, Communication using antennas fabricated in silicon integrated circuits, IEEE J. SolidState Circuits, 42, 1678, 10.1109/JSSC.2007.900236 Gutierrez, 2009, On-chip integrated antenna structures in CMOS for 60 GHz WPAN systems, IEEE J. Sel. Areas Commun., 27, 1367, 10.1109/JSAC.2009.091007 Shamim, 2014, Energy-efficient wireless network-on-chip architecture with log-periodic on-chip antennas, Proc. 24th Ed. Gt. Lakes Symp. VLSI - GLSVLSI’ 14, 85, 10.1145/2591513.2591566 Duato, 2002 Shamim, 2015, An interconnection architecture for seamless inter and intra-chip communication using wireless Links, Proc. 9th Int. Symp. Networks-on-Chip - NOCS’ 15, 1 Kagami, 2016, Efficient 3-D bus architectures for inductive-coupling ThruChip interfaces, IEEE Trans. Very Large Scale Integr. Syst., 24, 493, 10.1109/TVLSI.2015.2418216 Shamim, 2017, A wireless interconnection framework for seamless inter and intra-chip communication in multichip systems, IEEE Trans. Comput., 66, 389, 10.1109/TC.2016.2605093 Chang, 2012, Performance evaluation and design trade-offs for wireless network-on-chip architectures, ACM J. Emerg. Technol. Comput. Syst., 8, 1, 10.1145/2287696.2287706 2019 Zhang, 2005, Single-phase liquid cooled microchannel heat sink for electronic packages, Appl. Therm. Eng., 25, 1472, 10.1016/j.applthermaleng.2004.09.014 Lorenzini-Gutierrez, 2014, Variable fin density flow channels for effective cooling and mitigation of temperature nonuniformity in three-dimensional integrated circuits, J. Electron. Packag., 136, 21007, 10.1115/1.4027091 Pande, 2005, Performance evaluation and design trade-offs for network-on-chip interconnect architectures, IEEE Trans. Comput., 54, 1025, 10.1109/TC.2005.134 2019 Schantz, 2005, a near Field propagation law & a novel fundamental limit to antenna gain versus size, 2005 IEEE Antennas Propag. Soc. Int. Symp., 237, 10.1109/APS.2005.1552223 Huang, 2010, Interaction of scaling trends in processor architecture and cooling, 2010 26th Annu. IEEE Semicond. Therm. Meas. Manag. Symp., 198 Meng, 2012, Optimizing energy efficiency of 3-D multicore systems with stacked DRAM under power and thermal constraints, 648 Feero, 2009, Networks-on-chip in a three-dimensional environment: a performance evaluation, IEEE Trans. Comput., 58, 32, 10.1109/TC.2008.142 Binkert, 2011, The gem5 simulator, ACM SIGARCH, Comput. Archit. News, 39, 1, 10.1145/2024716.2024718 Woo, 1995, The SPLASH-2 programs: characterization and methodological considerations, Proc.22Nd Annu. Int. Symp. Comput. Archit., 24, 10.1109/ISCA.1995.524546 Bienia, 2011 Li, 2009, McPAT: an integrated power, area, and timing modeling framework for multicore and manycore architectures, 469 Jaussi, 2010, Multi-gbit I/O and interconnect co-design for power efficient links, 19th Top. Meet. Electr. Perform. Electron. Packag. Syst., 1 Yong, 2012, Signaling analysis of inter-chip I/O package routing for multi-chip package, 2012 4th Asia Symp. Qual. Electron. Des., 243, 10.1109/ACQED.2012.6320509