Evaluating speedups on distributed memory architectures

Parallel Computing - Tập 10 - Trang 247-253 - 1989
M Cosnard1,2, Y Robert1,2, B Tourancheau1,2
1CNRS, Laboratoire TIM3, Institut National Polytechnique de Grenoble, 38031 Grenoble Cedex, France
2Ecole Normale Supérieure de Lyon, Laboratoire d'Informatique, 69364 Lyon Cedex 07, France

Tài liệu tham khảo

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