Enhanced offset averaging technique for flash ADC design

Kattmann K, Barrow J. A technique for reducing differential nonlinearity errors in flash A/D converters. In: Proc. IEEE International Solid-State Circuits Con., San Francisco, CA, USA, 1997: 170–171. Wang Z-Y, Pan H, Chang C-M, et al. A 600 MSPS 8-bit folding ADC in 0.18μm CMOS. In: Tech. Digest, IEEE Symp. VLSI Circuits, 2004: 424–427. Mulder, 2004, A 21-mW 8-b 125-MSample/s ADC in 0.09-mm2 0.13-μm CMOS, IEEE Journal of Solid State Circuits, 39, 2116, 10.1109/JSSC.2004.836235 Scholtens, 2002, A 6-b 1.6-Gsample/s flash ADC in 0.18-μm CMOS using averaging termination, IEEE Journal of Solid-State Circuits, 37, 1599, 10.1109/JSSC.2002.804334 Sandner, 2005, A 6-bit 1.2-GS/s low-power flash-ADC in 0.13-μm digital CMOS, IEEE Journal of Solid-State Circuits, 40, 1499, 10.1109/JSSC.2005.847215 Jiang, 2005, A1-GHz signal bandwidth 6-bit CMOS ADC with power-efficient averaging, IEEE Journal of Solid State Circuits, 40, 532, 10.1109/JSSC.2004.841033 Pan, 1999