Energy-aware and fault-tolerant custom topology design method for network-on-chips

Hemani, 2000, Network on chip: an architecture for billion transistor era, 11 Dally, 2001, Route packets not wires: on-chip interconnection networks, 684 Benini, 2002, Networks on chips: a new soc paradigm, Computer, 35, 70, 10.1109/2.976921 Dally, 2004 Jantsch, 2003 Pande, 2013, Fixed latency on-chip interconnect for hardware spiking neural network architectures, Parallel Comput., 39, 357, 10.1016/j.parco.2013.04.010 Srinivasan, 2005, A technique for low energy mapping and routing in network-on-chip architectures, 387 Hu, 2003, Exploiting the routing flexibility for energy/performance aware mapping of regular noc architectures, 688 Murali, 2004, Bandwidth-constrained mapping of cores onto noc architectures, 20896 Tosun, 2012, Application-specific topology generation algorithms for network-on-chip design, IET Comput. Digit. Tech., 6, 318, 10.1049/iet-cdt.2011.0080 Chang, 2008, Low-power algorithm for automatic topology generation for application-specific networks on chips, IET Comput. Digit. Tech., 2, 239, 10.1049/iet-cdt:20070049 Srinivasan, 2006, Linear-programming-based techniques for synthesis of network-on-chip architectures, IEEE Trans. Very Large Scale Integr. (VLSI) Syst., 14, 407, 10.1109/TVLSI.2006.871762 Fick, 2009, A highly resilient routing algorithm for fault-tolerant nocs, 21 Gomez, 2004, An efficient fault-tolerant routing methodology for meshes and tori, IEEE Comput. Archit. Lett., 3, 10.1109/L-CA.2004.1 Ho, 2004, A new approach to fault-tolerant wormhole routing for mesh-connected parallel computers, IEEE Trans. Comput., 53, 427, 10.1109/TC.2004.1268400 Rodrigo, 2008, Efficient unicast and multicast support for cmps, 364 Wu, 2003, A fault-tolerant and deadlock-free routing protocol in 2d meshes based on odd-even turn model, IEEE Trans. Comput., 52, 1154, 10.1109/TC.2003.1228511 Pan, 2007, A framework for system reliability analysis considering both system error tolerance and component test quality, 1581 Constantinides, 2006, Bulletproof: a defect-tolerant cmp switch architecture, 5 Tosun, 2015, Fault-tolerant topology generation method for application-specific network-on-chips, IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst., 34, 1495, 10.1109/TCAD.2015.2413848 Li, 2017, Integer linear programming based fault-tolerant topology synthesis for application-specific noc, 96 Janidarmian, 2009, Onyx: a new heuristic bandwidth-constrained mapping of cores onto tile-based network on chip, IEICE Electron. Express, 6, 1, 10.1587/elex.6.1 Sahu, 2013, A survey on application mapping strategies for network-on-chip design, J. Syst. Archit., 59, 60, 10.1016/j.sysarc.2012.10.004 Huang, 2016, Floorplanning and topology synthesis for application-specific network-on-chips with rf-interconnect, ACM Trans. Des. Autom. Electron. Syst. (TODAES), 21, 40 Huang, 2015, Lagrangian relaxation based topology synthesis for application-specific network-on-chips, 1 Fick, 2009, Vicis: a reliable network for unreliable silicon, 812 Vitkovskiy, 2012, A dynamically adjusting gracefully degrading link-level fault-tolerant mechanism for nocs, IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst., 31, 1235, 10.1109/TCAD.2012.2188801 Aisopos, 2011, Ariadne: agnostic reconfiguration in a disconnected network environment, 298 Parikh, 2013, udirec: unified diagnosis and reconfiguration for frugal bypass of noc faults, 148 DiTomaso, 2014, Qore: a fault tolerant network-on-chip architecture with power-efficient quad-function channel (qfc) buffers, 320 S.P. Azad, B. Niazmand, J. Raik, G. Jervan, T. Hollstein, Holistic approach for fault-tolerant network-on-chip based many-core systems, arXiv preprint arXiv:1601.07089. Modarressi, 2011, Application-aware topology reconfiguration for on-chip networks, IEEE Trans. Very Large Scale Integr. (VLSI) Syst., 19, 2010, 10.1109/TVLSI.2010.2066586 Becker, 2012, Comparison of bio-inspired and graph-theoretic algorithms for design of fault-tolerant networks, 1 Becker, 2015, Evaluating heuristic optimization, bio-inspired and graph-theoretic algorithms for the generation of fault-tolerant graphs with minimal costs, 1033 Shah, 2017, Fault-tolerant application specific network-on-chip design, 1 Hu, 2005, Energy-and performance-aware mapping for regular noc architectures, IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst., 24, 551, 10.1109/TCAD.2005.844106 Pullini, 2007, Noc design and implementation in 65 nm technology, 273 Kim, 2011, Reducing network-on-chip energy consumption through spatial locality speculation, 233 International technology roadmap for semiconductors. URL http://www.itrs2.net/.