Energy–Delay Optimization of 64-Bit Carry-Lookahead Adders With a 240 ps 90 nm CMOS Design Example

Institute of Electrical and Electronics Engineers (IEEE) - Tập 44 Số 2 - Trang 569-583 - 2009
Radu Zlatanovici1, Sean Kao2, Borivoje Nikolić3
1Cadence Research Laboratories, Berkeley, CA
2Newport Media Inc., Lake Forest, CA
3Dept. of Electr. Eng. & Comput. Sci., Univ. of California Berkeley, Berkeley, CA

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