Design of crosstalk aware energy harvesting system-on-chip

Yan, 2021, Photovoltaic energy harvesting chip with P&O maximum power point tracking circuit and novel pulse-based multiplier, IEEE Trans Power Electron, 36, 12867, 10.1109/TPEL.2021.3082533 Sankar, 2022, An efficient inductive rectifier based piezo-energy harvesting using recursive pre-charge and accumulation operation, IEEE J Solid-State Circ, 57, 2404, 10.1109/JSSC.2022.3153590 Noulis, 2017, CMOS substrate coupling modeling and analysis flow for submicron SoC design, Analog Integr Circ Signal Process, 90, 477, 10.1007/s10470-016-0883-1 “Cadence Quantus.” https://www.cadence.com/en_US/home/tools/digital-design-and-signoff/silicon-signoff/quantus-extraction-solution.html. “ANSYS Totem.” https://www.ansys.com/products/semiconductors/ansys-totem. “Ansys HFSS.” https://www.ansys.com/products/electronics/ansys-hfss. “Momentum.” https://www.keysight.com/us/en/lib/resources/training-materials/momentum-key-features-1936424.html. “Sonnet.” https://www.sonnetsoftware.com/. Gan, 2015, Figures-of-merit to evaluate the significance of switching noise in analog circuits, IEEE Trans Very Large Scale Integr Syst, 23, 2945, 10.1109/TVLSI.2014.2386315 Meier, 2019, “Modeling Power Supply Noise Effects for System-Level Simulation of ΔΣ-ADCs”, SMACD 2019–16th Int, Conf Synth Model Anal Simul Methods Appl to Circuit Des Proc, 265 Suenaga, 2021, Compact simulation of chip-to-chip active noise coupling on a system PCB Board, IEEE Lett Electromagn Compat Pract Appl, 2, 15, 10.1109/LEMCPA.2020.2983687 Moursy, 2017, Efficient substrate noise coupling verification and failure analysis methodology for smart power ICs in automotive applications, IEEE Transactions on Power Electronics, 32, 5550, 10.1109/TPEL.2016.2604818 Karipidis, 2023, Simulation of substrate coupling for mobile communications SoC – A 20 GHz VCO case study, AEU - Int J Electron Commun, 161, 10.1016/j.aeue.2023.154548 Mandourarakis, 2022, Integrated maximum power point tracking system for photovoltaic energy harvesting applications, IEEE Transactions on Power Electronics, 37, 9865, 10.1109/TPEL.2022.3156400 V. Gavriilidou, A. Voulkidou, T. Noulis, N. Codreanu, and C. Ionescu, “System on Chip Noise Integrity Simulation,” pp. 14–29, 2022. Umar, 2021, Bondwire Model and Compensation Network for 60 GHz Chip-to-PCB Interconnects, IEEE Antennas and Wireless Propagation Letters, 20, 2196, 10.1109/LAWP.2021.3108499 Jin, 2018, Analytical equivalent circuit modeling for BGA in high-speed package, IEEE Transactions on Electromagnetic Compatibility, 60, 68, 10.1109/TEMC.2017.2726560 Ndip, 2013, “Modeling and minimizing the inductance of bond wire interconnects”, 2013 17th IEEE Work, Signal Power Integrity, SPI, 2013, 1 V. Gogolou, K. Kozalakis, T. Noulis, and S. Siskos, “Chip-Package-Board Co-Design Methodology for Energy Harvesting DC – DC Boost Converters,” pp. 1–5, 2022. V. Gogolou, K. Kozalakis, T. Noulis, and S. Siskos, “Integrated DC - DC converter design methodology for design cycle speed up,” Integration, vol. 88, no. June 2022, pp. 80–90, 2023, doi: 10.1016/j.vlsi.2022.09.003. Perumal, 2019, New approaches for Delaunay triangulation and optimisation, Heliyon, 5, e02319, 10.1016/j.heliyon.2019.e02319 “Cadence Spectre.” https://www.cadence.com/en_US/home/tools/custom-ic-analog-rf-design/circuit-simulation/spectre-simulation-platform.html. B. T. Lynch, “Under the Hood of a DC / DC Boost Converter,” Texas Instruments Power Supply Des. Semin., pp. 3–26, 2002, [Online]. Available: http://www.ti.com/download/trng/docs/seminar/Topic_3_Lynch.pdf. Meade, 2008, Parasitic inductance effect on switching losses for a high frequency Dc-Dc converter, Conf Proc - IEEE Appl Power Electron Conf Expo - APEC, 3 Locorotondo E, Pugi L, Corti F, Becchi L, Grasso F. Analytical Model of Power MOSFET Switching Losses due to Parasitic Components. In: 2019 IEEE 5th international forum on research and technology for society and industry (RTSI); Sep. 2019. p. 331–336. doi: 10.1109/RTSI.2019.8895562.