DRAM performance as a function of its structure and memory stream locality

Microprocessors and Microsystems - Tập 28 - Trang 57-68 - 2004
Juha Alakarhu1, Jarkko Niittylahti1
1Institute of Digital and Computer Systems, Tampere University of Technology, P.O. Box 553, FIN-33101 Tampere, Finland

Tài liệu tham khảo

Lin, 2001, Designing a modern memory hierarchy with hardware prefetching, IEEE Transactions Computers, 50, 1202, 10.1109/12.966495 Wulf, 1995, Hitting the memory wall: implications of the obvious, Computer Architecture News, 23, 20, 10.1145/216585.216588 Burger, 1996, Memory bandwidth limitations of future microprocessors, Computer Architecture News, 27, 78, 10.1145/232974.232983 Cuppu, 2001, Concurrency, latency, or system overhead: Which has the largest impact on uniprocessor DRAM-system performance? Cuppu, 2001, High-performance DRAMs in workstation environments, IEEE Transactions Computers, November Davis, 2000 Dipert, 2000, Slammin ‘jammin’ DRAM scramble, EDN, 68 Sato, 1998, Fast cycle ram (FCRAM); a 20-ns random row access, pipe-lined operating dram Kangmin, 2001, A comparative performance analysis of a DDR-SDRAM, a D-RDRAM, and a DDR-FCRAM using a POPeye simulator Cuppu, 1999, A performance comparison of contemporary DRAM architectures McKee, 2000, Dynamic access ordering for streamed computations, IEEE Transactions Computers, 49, 1255, 10.1109/12.895941 Alakarhu, 2002, DRAM simulator for design and analysis of digital systems, Microprocessors and Microsystems, 26, 189, 10.1016/S0141-9331(02)00013-3 Weikle, 1998, Caches as filters: a new approach to cache analysis, Proc. 6th International Symposium on Modeling, Analysis and Simulation of Computer and Telecom Systems, 2, 10.1109/MASCOT.1998.693668 D. Burger, T.M. Austin. The SimpleScalar tool set, version 2.0. Technical report, Computer Sciences Department, University of Wisconsin, 1997. Alakarhu, 2002, Quick memory stream locality analysis Alakarhu, 2002, A comparison of precharge policies with modern DRAM architectures Micron Technology Inc. Double Data Rate (DDR) SDRAM 256Mb:x4, x8, x16 Preliminary, 2001. Patterson, 1998 Conte, 1990, Benchmark characterization for experimental system evaluation Mattson, 1970, Evaluation techniques for storage hierarchies, IBM Systems Journal, 9, 78, 10.1147/sj.92.0078 John, 1998 J. Alakarhu, Introduction to Spatial and Temporal Locality Analyzers. 2003. Zhang, 2000, A permutation-based page interleaving scheme to reduce row-buffer conflicts and exploit data locality Alakarhu, 2002, Introduction to the Rascas Memory Simulator, Introduction to the Rascas Memory Simulator