Customizing completely specified pattern set targeting dynamic and leakage power reduction during testing

Schulz, 1988, Socrates: a highly efficient automatic test pattern generation system, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 7, 126, 10.1109/43.3140

S. Kajihara, I. Pomeranz, K. Kinoshita, S.M. Reddy, Cost-effective generation of minimal test sets for stuck-at faults in combinational logic circuits, in: Proceedings of the 30th Conference on Design Automation, June 1993, pp. 102–106.

Neophytou, 2010, Test set generation with a large number of unspecified bits using static and dynamic techniques, IEEE Transactions on Computers, 59, 301, 10.1109/TC.2009.178

S. Kajihara, Kohei Miyase, On identifying don't care inputs of test patterns for combinational circuits, in: Proceedings of the 2001 International Conference on Computer-Aided Design (ICCAD '01), November 2001, pp. 364–369.

Miyase, 2004, XID: don't care identification of test patterns for combinational circuits, IEEE Transactions on Computer-Aided Design of Integrated Circuits And Systems, 23, 321, 10.1109/TCAD.2003.822103

El-Maleh Aiman, Al-Suwaiyan Ali, An efficient test relaxation technique for combinational and full-scan sequential circuits, in: Proceedings of the 20th IEEE VLSI Test Symposium, April 2002, pp. 53–59.

Bushnell, 2000

Abramovici, 1990

Girard, 2002, Survey of low-power testing of VLSI circuits, IEEE Design and Test of Computers, 19, 82, 10.1109/MDT.2002.1003802

Ravi, 2007, Power-aware test: challenges and solutions, IEEE International Test Conference, 1

Dabholkar, 1998, Techniques for minimizing power dissipation in scan and combinational circuits during test application, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 7, 1325, 10.1109/43.736572

P. Girard, L. Guiller, C. Landrault, S. Pravossoudovitch, A. Test, Vector ordering technique for switching activity reduction during test operation, in: Proceedings of the 9th Great Lakes Symposium on VLSI, March 1999, pp. 24–27.

X. Kavousianos, D. Bakalis, M. Bellos, D. Nikolos, An efficient test vector ordering method for low power testing, in: Proceedings of the IEEE Computer Society Annual Symposium on VLSI, February 2004, pp. 285–288.

Emrah Acar, Anirudh Devgan, Sani R. Nassif, Leakage and leakage sensitivity computation for combinational circuits, in: Proceedings of the 2003 International Symposium on Low Power Electronics and Design, August 2003, pp. 96–99.

Johnson, 1999, Models and algorithms for bounds on leakage in CMOS circuits, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 18, 714, 10.1109/43.766723

Yu-Shiang Lin, D. Sylvester, Runtime leakage power estimation technique for combinational circuits, in: Proceedings of the 12th Asia and South Pacific Design Automation Conference, January 2007, pp. 660–665.

S. Kundu, S. Chattopadhyay, K. Manna, A. Novel, Technique to reduce both leakage and peak power during scan testing, in: Proceedings of the 2008 IEEE Region 10 and the Third international Conference on Industrial and Information Systems, December 2008, pp. 1–6.

Lee, 1996, HOPE: an efficient parallel fault simulator for synchronous sequential circuits, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 1048

〈http://www.faraday.com.tw/AIP/ips/90library.html〉 as on 17 January 2011.

David, 2002

Cadence Virtuoso Analog Design Environment User Guide, Product Version 5.1.41, July 2007.

Kennedy, 1995, Particle swarm optimization, IEEE International Conference on Neural Networks 1995, 4, 1942

Wang, 2003, Particle swarm optimization for traveling salesman problem, International Conference on Machine Learning and Cybernetics, 2003, 3, 1583, 10.1109/ICMLC.2003.1259748

Shi, 1998

H.K. Lee, D.S. Ha, Atalanta: An Efficient ATPG for Combinational Circuits, Technical Report, 93-12, Department of Electrical Engineering, Virginia Polytechnic Institute and State University, Blacksburg, Virginia, 1993.

TetraMAX® ATPG User Guide, Version X-2005.09, Synopsys, September 2005.

V.R., Devanathan, C.P. Ravikumar, V. Kamakoti, PMScan: a power-managed scan for simultaneous reduction of dynamic and leakage power during scan test, in: Proceedings of the International Test Conference, vol. 1, October 2007, pp. 358–366.

Wang, 1998, ATPG for heat dissipation minimization during test application, IEEE Transactions on Computers, 47, 256, 10.1109/12.663775

Xiaoqing Wen, Yoshiyuki Yamashita, Seiji Kajihara, Laung-Terng Wang, Kewal K. Saluja, Kozo Kinoshita, On low-capture-power test generation for scan testing, in: Proceedings of the 23rd IEEE VLSI Test Symposium (VTS'05), May 2005, pp. 265–270.

S. Sharifi, J. Jaffari, M. Hosseinabady, A. Afzali-Kusha, Z. Navabi, Simultaneous reduction of dynamic and static power in scan structures, in: Proceedings of the Design, Automation and Test in Europe, vol. 2, March 2005, pp. 846–851.

Paulo F. Flores, J. Costa, H. Neto, J. Monteiro, Joao P. Marques Silva, Assignment and reordering of incompletely specified pattern sequences targetting minimum power dissipation, in: Proceedings of the 12th International Conference on VLSI Design—VLSI for the Information Appliance, January 1999, pp. 37–41.

S. Chattopadhyay, N. Choudhary, Genetic algorithm based approach for low power combinational circuit testing, in: Proceedings of the 16th International Conference on VLSI Design, January 2003, pp. 552–557.