Controller Resynthesis for Testability Enhancement of RTL Controller/Data Path Circuits

Springer Science and Business Media LLC - Tập 13 - Trang 201-212 - 1998
Srivaths Ravi1, Indradeep Ghosh2, Rabindra K. Roy3, Sujit Dey4
1Department of Electrical Engineering, Princeton University, Princeton
2Fujitsu Labs of America, Sunnyvale
3Strategic CAD Lab, Intel Corporation, Hillsboro
4Department of ECE, University of California, San Diego

Tóm tắt

In this paper, we propose a controller resynthesis technique to enhance the testability of register-transfer level (RTL) controller/data path circuits. Our technique exploits the fact that the control signals in an RTL implementation are don't cares under certain states/conditions. We make an effective use of the don't care information in the controller specification to improve the overall testability (better fault coverage and shorter test generation time). If the don't care information in the controller specification leaves little scope for respecification, we add control vectors to the controller to enhance the testability. Experimental results with example benchmarks show an average increase in testability of 9% with a 3–4 fold decrease in test generation time for the modified implementation. The area, delay and power overheads incurred for testability are very low. The average area overhead is 0.4%, and the average power overhead is 4.6%. There was no delay overhead due to this technique in most of the cases.

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Springer Science and Business Media LLC

Tập 13

201-212

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