Comparison of high-performance VLSI adders in the energy-delay space
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Tài liệu tham khảo
naffziger, 1996, a sub-nanosecond 0.5 <formula><tex>$\mu{\hbox {m}}$ </tex></formula> 64-b adder design, Proc IEEE Int Solid-State Circuits Conf Dig Tech Papers, 362
park, 0, 470 ps 64-bit parallel binary adder, Proc Symp VLSI Circuits Dig Tech Papers, 192
oklobdzija, 2003, energy-delay estimation technique for high-performance microprocessor vlsi adders, Proc 16th Int Symp Computer Arithmetic, 272, 10.1109/ARITH.2003.1207688
0, HSPICE User s Guide
sutherland, 1999, Logical Effort Designing Fast CMOS Circuits
sutherland, 1991, logical effort: designing for speed on the back of an envelop, Advanced Research in VLSI
dao, 2001, application of logical effort techniques for speed optimization and analysis of representative adders, Proc 35th Annu Asilomar Conf Signals Systems and Computers, 1666
han, 1987, vlsi design of high-speed low-area addition circuitry, Proc IEEE Int Conf Computer Design VLSI in Computers and Processors, 418
