Classification of analog synthesis tools based on their architecture selection mechanisms

Integration - Tập 41 - Trang 238-252 - 2008
E. Martens1, G. Gielen1
1Department of Electrical Engineering ESAT–MICAS, Katholieke Universiteit Leuven, Kasteelpark Arenberg 10, B–3001 Heverlee, Belgium

Tài liệu tham khảo

Sansen, 2006 Gielen, 2000, Computer-aided design of analog and mixed-signal integrated circuits, Proc. IEEE, 88, 1825, 10.1109/5.899053 Ranjan, 2004, Fast, layout-inclusive analog circuit synthesis using pre-compiled parasitic-aware symbolic performance models, 604 Zhang, 2004, A synthesis flow toward fast parasitic closure for radio-frequency integrated circuits, 155 del Mar Hershenson, 2001, Optimal design of a CMOS op-amp via geometric programming, IEEE Trans. Comput.-Aided Des. Integrated Circuits, 20, 1, 10.1109/43.905671 Harjani, 1989, OASYS: a framework for analog circuit synthesis, IEEE Trans. Comput.-Aided Des., 8, 1247, 10.1109/43.44506 Koh, 1990, OPASYN: A compiler for CMOS operational amplifiers, IEEE Trans. Comput.-Aided Des., 9, 113, 10.1109/43.46777 Van der Plas, 2001, AMGIE—A synthesis environment for CMOS analog integrated circuits, IEEE Trans. Comput.-Aided Des. Integrated Circuits, 20, 1037, 10.1109/43.945301 Kruiskamp, 1995, DARWIN, 433 Koza, 1997, Automated synthesis of analog electrical circuits by means of genetic programming, IEEE Trans. Evol. Comput., 1, 109, 10.1109/4235.687879 Doboli, 2003, Exploration-based high-level synthesis of linear analog systems operating at low/medium frequencies, IEEE Trans. Comput.-Aided Des. Integrated Circuits, 22, 1556, 10.1109/TCAD.2003.818374 Huelsman, 1993, Optimization—A powerful tool for analysis and design, IEEE Trans. Circuits Syst.—I: Fundam. Theor. Appl., 40, 431, 10.1109/81.257298 Binder, 2004, A study on global and local optimization techniques for TCAD analysis tasks, IEEE Trans. Comput.-Aided Des. Integrated Circuits, 23, 814, 10.1109/TCAD.2004.828130 Carley, 1996, Synthesis tools for mixed-signal ICs, 298 De Smedt, 2003, Watson: design space boundary exploration and model generation for analog and RF IC design, IEEE Trans. Comput.-Aided Des. Integrated Circuits, 22, 213, 10.1109/TCAD.2002.806598 De Ranter, 2002, CYCLONE: automated design and layout of RF LC-oscillators, IEEE Trans. Comput.-Aided Des. Integrated Circuits, 21, 1161, 10.1109/TCAD.2002.802267 Nieuwoudt, 2006, SOC-NLNA, 879 Vassiliou, 1996, A video driver system designed using a top-down constraint-driven methodology, 463 Crols, 1995, A high-level design and optimization tool for analog RF receiver front-ends, 550 Degrauwe, 1987, IDAC: an interactive design tool for analog CMOS circuits, IEEE J. Solid-State Circuits, 22, 1106, 10.1109/JSSC.1987.1052861 Torralba, 1996, FASY: a fuzzy-logic based tool for analog synthesis, IEEE Trans. Comput.-Aided Des. Integrated Circuits, 15, 705, 10.1109/43.503939 Stehr, 2004, Analog performance space exploration by Fourier–Motzkin elimination with application to hierarchical sizing, 847 Medeiro, 1997, Using CAD tools for shortening the design cycle of high-performance sigma–delta modulators: a 16.4 bit, 9.6kHz, 1.71MW ΣΔM in CMOS 0.7μm Technology, Int. J. Circuit Theory Appl., 25, 319, 10.1002/(SICI)1097-007X(199709/10)25:5<319::AID-CTA976>3.0.CO;2-U Vogels, 2003, Architectural Selection of A/D Converters, 974 Zitzler, 1999, Multiobjective Evolutionary Algorithms: a comparative case study and the strength pareto approach, IEEE Trans. Evol. Comput., 3, 257, 10.1109/4235.797969 Fletcher, 1987 Phelps, 2000, Anaconda: simulation-based synthesis of analog circuits via stochastic pattern search, IEEE Trans. Comput.-Aided Des. Integrated Circuits, 19, 703, 10.1109/43.848091 Graeb, 2001, The sizing rules method for analog integrated circuit design, 343 Vancorenland, 2000, Optimal RF design using smart evolutionary algorithms, 7 Liu, 2002, Remembrance of circuit past, 437 Bowman, 1985, A knowledge-based system for analog integrated circuit design, 210 Sheu, 1988, A knowledge-based approach to analog IC design, IEEE Trans. Circuits Syst., 35, 256, 10.1109/31.1735 O’Connor, 1998, Automated design of switched-current cells, 477 Harvey, 1992, STAIC: an interactive framework for synthesizing CMOS and BiCMOS analog circuits, IEEE Trans. Comput.-Aided Des., 11, 1402, 10.1109/43.177403 Fares, 1995, FPAD: a fuzzy nonlinear programming approach to analog circuit design, IEEE Trans. Comput.-Aided Des. Integrated Circuits, 14, 785, 10.1109/43.391726 Onodera, 1990, Operational-amplifier compilation with performance optimization, IEEE J. Solid-State Circuits, 25, 466, 10.1109/4.52171 Nagaraj, 1993, A new optimizer for performance optimization of analog integrated circuits, 148 Nye, 1988, DELIGHT.SPICE: an optimization-based system for the design of integrated circuits, IEEE Trans. Comput.-Aided Des., 7, 501, 10.1109/43.3185 Antreich, 1994, Circuit analysis and optimization driven by worst-case distances, IEEE Trans. Comput.-Aided Des. Integrated Circuits, 13, 57, 10.1109/43.273749 Antreich, 1988, Nominal design of integrated circuits on circuit level by an interactive improvement method, IEEE Trans. Circuits Syst., 35, 1501, 10.1109/31.9913 Ren, 2005, A unified optimization framework for equalization filter synthesis, 638 Bhattacharya, 2004, Correct-by-construction layout-centric retargeting of large analog designs, 139 Conn, 1998, JiffyTune: circuit optimization using time-domain sensitivities, IEEE Trans. Comput.-Aided Des. Integrated Circuits, 17, 1292, 10.1109/43.736569 Shyu, 1988, Optimization-based transistor sizing, IEEE J. Solid-State Circuits, 23, 400, 10.1109/4.1000 Maulik, 1993, Sizing of cell-level analog circuits using constrained optimization techniques, IEEE J. Solid-State Circuits, 28, 233, 10.1109/4.209989 Damera-Venkata, 1999, An automated framework for multicriteria optimization of analog filter designs, IEEE Trans. Circuits Syst.—II: Analog Digital Signal Process., 46, 981, 10.1109/82.782038 Dharchoudhury, 1992, An integrated approach to realistic worst-case design optimization of MOS analog circuits, 704 Antreich, 2000, WiCkeD, 511 Mandal, 2001, CMOS op-amp sizing using a geometric programming formulation, IEEE Trans. Comput.-Aided Des. Integrated Circuits, 20, 22, 10.1109/43.905672 del Mar Hershenson, 2002, Design of pipeline analog-to-digital converters via geometric programming, 317 Dawson, 2001, Optimal allocation of local feedback in multistage amplifiers via geometric programming, IEEE Trans. Circuits Syst.—I: Fundam. Theor. Appl., 48, 1, 10.1109/81.903183 Kim, 2004, Techniques for improving the accuracy of geometric-programming based analog circuit design optimization, 863 Li, 2004, Robust analog/RF circuit design with projection-based posynomial modeling, 855 Xu, 2005, OPERA, 632 Daems, 2003, Simulation-based generation of posynomial performance models for the sizing of analog integrated circuits, IEEE Trans. Comput.-Aided Des. Integrated Circuits, 22, 517, 10.1109/TCAD.2003.810742 Vanderhaegen, 2004, Automated design of operational transconductance amplifiers using reversed geometric programming, 133 Ju, 1991, Consistency checking and optimization of macromodels, IEEE Trans. Comput.-Aided Des., 10, 957, 10.1109/43.85733 Mehrotra, 1994, Stochastic optimization approach to transistor sizing for CMOS VLSI circuits, 36 Styblinski, 1986, Algorithms and software tools for IC yield optimization based on fundamental fabrication Parameters, IEEE Trans. Comput.-Aided Des., 5, 79, 10.1109/TCAD.1986.1270179 Gielen, 1990, Analog circuit design optimization based on symbolic simulation and simulated annealing, IEEE J. Solid-State Circuits, 25, 707, 10.1109/4.102664 Ochotta, 1996, Synthesis of high-performance analog circuits in ASTRX/OBLX, IEEE Trans. Comput.-Aided Des. Integrated Circuits, 15, 273, 10.1109/43.489099 Medeiro, 1994, A statistical optimization-based approach for automated sizing of analog cells, 594 Yuan, 2005, GBOPCAD: a synthesis tool for high-performance gain-boosted opamp design, IEEE Trans. Circuits Syst.—I: Regular Pap., 52, 1535, 10.1109/TCSI.2005.851718 Ruiz-Amaya, 2005, High-level synthesis of switched-capacitor switched-current and continuous-time ΣΔ modulators using SIMULINK-based time-domain behavioral models, IEEE Trans. Circuits Syst.—I: Regular Pap., 52, 1795, 10.1109/TCSI.2005.852479 Rijmenants, 1989, ILAC: an automated layout tool for analog CMOS circuits, IEEE J. Solid-State Circuits, 24, 417, 10.1109/4.18603 Cohn, 1991, KOAN/ANAGRAM II: new tools for device-level analog placement and routing, IEEE J. Solid-State Circuits, 26, 330, 10.1109/4.75012 Lampaert, 1995, A performance-driven placement tool for analog integrated circuits, IEEE J. Solid-State Circuits, 30, 773, 10.1109/4.391116 Malavasi, 1996, Automation of IC layout with analog constraints, IEEE Trans. Comput.-Aided Des. Integrated Circuits, 15, 923, 10.1109/43.511572 Krasnicki, 2001, ASF, 350 Zhang, 2006, Placement algorithm in analog-layout designs, IEEE Trans. Comput.-Aided Des. Integrated Circuits, 25, 1889, 10.1109/TCAD.2005.860957 Back, 1997, Evolutionary computation: comments on the history and current state, IEEE Trans. Evol. Comput., 1, 3, 10.1109/4235.585888 Koza, 1992 Price, 2005 Nam, 2001, Parameter optimization of an on-chip voltage reference circuit using evolutionary programming, IEEE Trans. Evol. Comput., 5, 414, 10.1109/4235.942535 Vaz, 2002, Design of low-voltage CMOS pipelined ADC's using 1 pico-Joule of energy per conversion, 921 Wolfe, 2003, Extraction and use of neural network models in automated synthesis of operational amplifiers, IEEE Trans. Comput.-Aided Des. Integrated Circuits, 22, 198, 10.1109/TCAD.2002.806600 Alpaydın, 2003, An evolutionary approach to automatic synthesis of high-performance analog integrated circuits, IEEE Trans. Evol. Comput., 7, 240, 10.1109/TEVC.2003.808914 Ramos, 2005, An efficient fully parasitic-aware power amplifier design optimization tool, IEEE Trans. Circuits Syst.—I: Regular Pap., 52, 1526, 10.1109/TCSI.2005.851677 Chu, 2005, Elitist nondominated sorting genetic algorithm based RF IC optimizer, IEEE Trans. Circuits Syst.—I: Regular Pap., 52, 535, 10.1109/TCSI.2004.842427 Maulik, 1995, Integer programming based topology selection of cell-level analog circuits, IEEE Trans. Comput.-Aided Des. Integrated Circuits, 14, 401, 10.1109/43.372366 Fung, 1989, Self-reconstructing technique for expert system-based analog IC designs, IEEE Trans. Circuits Syst., 36, 318, 10.1109/31.20216 El-Turky, 1989, BLADES: An artificial intelligence approach to analog circuit design, IEEE Trans. Comput.-Aided Des., 8, 680, 10.1109/43.31523 Toumazou, 1995, Analog IC design automation: Part I—automated circuit generation: new concepts and methods, IEEE Trans. Comput.-Aided Des. Integrated Circuits, 14, 218, 10.1109/43.370422 Ning, 1991, SEAS, 5.2.1 McConaghy, 2007, Simultaneous multi-topology multi-objective sizing across thousands of analog circuit topologies, 944 Eeckelaert, 2006, Hierarchical bottom–up analog optimization methodology validated by a delta–sigma A/D converter design for the 802.11a/b/g Standard, 25 Tang, 2006, High-level synthesis of ΔΣ modulator topologies optimized for complexity, sensitivity, and power consumption, IEEE Trans. Comput.-Aided Des. Integrated Circuits, 25, 597, 10.1109/TCAD.2005.854633 Francken, 2003, A high-level simulation and synthesis environment for ΔΣ modulators, IEEE Trans. Comput.-Aided Des. Integrated Circuits, 22, 1049, 10.1109/TCAD.2003.814954 Achyuthan, 1994, Mixed analog/digital hardware synthesis of artificial neural networks, IEEE Trans. Comput.-Aided Des. Integrated Circuits, 13, 1073, 10.1109/43.310897 Horta, 1997, Algorithm-driven synthesis of data conversion architectures, IEEE Trans. Comput.-Aided Des. Integrated Circuits, 16, 1116, 10.1109/43.662675 Antoa, 1995, ARCHGEN: automated synthesis of analog systems, IEEE Trans. VLSI Syst., 3, 231, 10.1109/92.386223 Chang, 1996 Martens, 2006, Top-down heterogeneous synthesis of analog and mixed-signal systems, 275 Lauwers, 2002, Power estimation methods for analog circuits for architectural exploration of integrated systems, IEEE Trans. VLSI Syst., 10, 155, 10.1109/92.994993 Doboli, 2004, A two-layer library-based approach to synthesis of analog systems from VHDL-AMS specifications, ACM Trans. Des. Automat. Electron. Syst., 9, 238, 10.1145/989995.990000 Haigh, 2005, Systematic synthesis of active-RC circuit building-blocks, Analog Integrated Circuits Signal Process., 43, 297, 10.1007/s10470-005-1609-y Oehler, 2002, A methodology for system-level synthesis of mixed-signal applications, IEEE Trans. VLSI Syst., 10, 935, 10.1109/TVLSI.2002.801577 Lohn, 1999, A circuit representation technique for automated circuit design, IEEE Trans. Evol. Comput., 3, 205, 10.1109/4235.788491 Bruccoleri, 2001, Generating All two-MOS transistor amplifiers leads to new wide-band LNAs, IEEE J. Solid-State Circuits, 36, 1032, 10.1109/4.933458 Klumperink, 2003, Systematic comparison of HF CMOS Transconductors, IEEE Trans. Circuits Systems—II: Analog Digital Signal Process., 50, 728, 10.1109/TCSII.2003.818393 Sripramong, 2002, The invention of CMOS amplifiers using genetic programming and current-flow analysis, IEEE Trans. Comput.-Aided Des. Integrated Circuits, 21, 1237, 10.1109/TCAD.2002.804109 De Man, 1988, CATHEDRAL-II—a computer-aided synthesis system for digital signal processing VLSI systems, IEE Comput.-Aided Eng. J., 5, 55, 10.1049/cae.1988.0015