Challenges of 22 nm and beyond CMOS technology

Science in China Series F: Information Sciences - Tập 52 - Trang 1491-1533 - 2009
Ru Huang1, HanMing Wu2, JinFeng Kang1, DeYuan Xiao2, XueLong Shi2, Xia An1, Yu Tian1, RunSheng Wang1, LiangLiang Zhang1, Xing Zhang1, YangYuan Wang1
1Department of Microelectronics, Peking University, Beijing, China
2Semiconductor Manufacturing International Corporation (SMIC), Beijing, China

Tóm tắt

It is predicted that CMOS technology will probably enter into 22 nm node around 2012. Scaling of CMOS logic technology from 32 to 22 nm node meets more critical issues and needs some significant changes of the technology, as well as integration of the advanced processes. This paper will review the key processing technologies which can be potentially integrated into 22 nm and beyond technology nodes, including double patterning technology with high NA water immersion lithography and EUV lithography, new device architectures, high K/metal gate (HK/MG) stack and integration technology, mobility enhancement technologies, source/drain engineering and advanced copper interconnect technology with ultra-low-k process.

Tài liệu tham khảo

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