Architecture of an Image Rendering Co-Processor for MPEG-4 Visual Compositing

Journal of VLSI signal processing systems for signal, image and video technology - Tập 31 - Trang 157-171 - 2002
M. Berekovic1, P. Pirsch1, T. Selinger2, K.-I.- Wels2, C. Miro3, A. Lafage3, C. Heer4, G. Ghigo5
1Laboratorium für Informationstechnologie, Universität Hannover, Germany
2Heinrich-Hertz-Institut, Berlin, Germany
3ENST, Paris, France
4Infineon AG, München, Germany
5TILAB, Torino, Italy

Tóm tắt

The TANGRAM VLSI co-processor is intended as a building block for use in system-on-chip (SOC) designs for the versatile MPEG-4 multimedia standard. It is designed to perform the computation intensive final step of MPEG-4 video decoding: compositing of scenes at the display. This includes warping and alpha blending of multiple full-screen video textures in real-time. TANGRAM consists of a RISC control processor and multiple powerful arithmetic units that perform rendering calculations directly in hardware. This hybrid architecture enables adaptation to changes in algorithms or support for different video-formats in software. Communication to a host CPU and video decoding hardware is done via the very common PI-bus on-chip interface. TANGRAM directly interfaces with the ITU-R601/656 digital video output. VHDL implementation and synthesis for a 0.35 μ standard-cell library provide an estimate of 100 MHz achievable clock frequency (worst-case), 52 mm2 overall area and 1 Watt power dissipation. TANGRAM has sufficient performance for rendering of MPEG-4 Main Profile@Layer3 scenes (ITU-R 601).

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Tài liệu tham khảo

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Thông tin xuất bản

Journal of VLSI signal processing systems for signal, image and video technology

Tập 31

157-171

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