An ultra-efficient design and optimized energy dissipation of reversible computing circuits in QCA technology using zone partitioning method
Tóm tắt
Quantum-dot Cellular Automata (QCA) is an alternative step towards semiconductor-based CMOS technology. The QCA nanotechnology has a very fast circuit speed, ultra-low power consumption, minimum energy dissipation, extremely high switching frequency, and very small size in nanometer (nm) than traditional transistor-based CMOS technology. QCA technology plays an important role in the field of computational, communication, and information technology. In this paper, we have presented an experimental coplanar single layer reversible logic gates (RLG) such as Feynman gate (FG) and Double Feynman gate (F2G) implementation by using a bijective functional algorithm and demonstrated the zone partitioning problems, which are related to the synchronization of the clock. An optimized the energy dissipation of proposed circuit’s by QCADesigner-E (QD-E) version 2.2 tool. The presented reversible computational logic gates such as FG and F2G utilized 43.47% and 32.50% less number of design QCA cells, and 37.50% and 37.77% reduce the total design area respectively as compared to an existing optimal design. The proposed synchronization clocking method has outstanding characteristics such as reduced total design area, cell area, and latency, low complexity of circuits, and ultra-high-speed of proposed implemented designs.
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