An analytical model for the surface potential and threshold voltage of a double-gate heterojunction tunnel FinFET
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Dennard, R., Gaensslen, F., Yu, H., Rideout, V., Bassous, E., LeBlanc, A.: Design of ion-implanted MOSFETs with very small physical dimensions. IEEE J. Solid State Circuits 9, 256–268 (1974)
Lo, S., Buchanan, D., Taur, Y., Wang, W.: Quantum-mechanical modeling of electron tunneling current from the inversion layer of ultra-thin-oxide nMOSFET’s. IEEE Electron Device Lett. 18, 209–212 (1997)
Tanaka, T., Usuki, T., Futatsugi, T., Momiyama, Y., Sugii T.: Vth fluctuation induced by statistical variation of pocket dopant profile. In: IEEE International Electron Devices Meeting, pp. 271–274 (2000)
Kahng, D., Atalla, M.: Silicon–silicon dioxide field induced surface devices. In: IRE-AIEE Solid-State Device Research Conference (1960)
Dennard, R., Gaensslen, F., Kuhn, L., Yu, H.: Design of micron MOS switching devices. In: IEDM Tech. Dig., pp. 168–170 (1972)
Maity, N.P., Maity, R., Baishya, S.: Voltage and oxide thickness dependent tunneling current density and tunnel resistivity model: application to high-k material HfO2 based MOS devices. Superlattices Microstruct. 111, 628–641 (2017)
Maity, N.P., Maity, R., Thapa, R.K., Baishya, S.: A tunneling current density model for ultra thin HfO2 high-k dielectric material based MOS devices. Superlattices Microstruct. 95, 24–32 (2016)
Frank, D., Dennard, R., Nowak, E., Solomon, P., Taur, Y., Wong, H.: Device scaling limits of Si MOSFETs and their application dependencies. Proc. IEEE 89, 259–288 (2001)
Lee, J., Cho, H., Kang, C., Rhee, S., Kim, Y., Choi, R., Kang, C., Choi, C., Akbar, M.: High-k dielectrics and MOSFET characteristics. In: IEDM Tech. Dig., pp. 95–98 (2003)
Huang, X., Lee, X., Kuo, C., Hisamoto, D., Chang, L., Kedzierski, J., Anderson, E., Takeuchi, H., Choi, Y., Asano, K., Subramanian, V., King, T., Bokor, J., Hu, C.: Sub 50-nm FinFET: PMOS. In: IEDM Tech. Dig., pp. 341–344 (1999)
Koley, K., Dutta, A., Saha, S., Sarkar, C.K.: Analysis of high-k spacer asymmetric underlap DG-MOSFET for SOC application. IEEE Trans. Electron Devices 62, 1733–1739 (2015)
Gaynor, B., Hassoun, S.: Fin shape impact on FinFET leakage with application to multithreshold and ultralow-leakage FinFET design. IEEE Trans. Electron Devices 61, 2738–2745 (2014)
Hong, Y., Guo, Y., Yang, H., Yao, J., Zhang, J., Ji, X.: A novel bulk- FinFET with dual-material gate. In: IEEE International Conference on Solid-State and Integrated Circuit Technology (2014)
Riddit, C., Alexander, C., Brown, A., Roy, S., Asenov, A.: Simulation of “Ab Initio” quantum confinement scattering in UTB MOSFETs using three-dimensional ensemble Monte Carlo. IEEE Trans. Electron Devices 58, 600–609 (2011)
Lattanzio, L., Micheilis, L., Ionescu, A.: Complementary germanium electron–hole bilayer tunnel FET for sub-0.5-V operation. IEEE Electron Device Lett. 33, 167–170 (2012)
Ortiz-Conde, A., Sucre-González, A., Torres-Torres, R., Molina, J., Murphy-Arteaga, R., García-Sánchez, F.: Conductance-to-current-ratio-based parameter extraction in MOS leakage current models. IEEE Trans. Electron Devices 63, 3844–3850 (2016)
Lu, H., Taur, Y.: An analytic potential model for symmetric and asymmetric DG MOSFETs. IEEE Trans. Electron Devices 53, 1161–1169 (2006)
Shih, C., Chien, N.: Sub-10-nm tunnel field-effect transistor with graded Si/Ge heterojunction. IEEE Electron Device Lett. 32, 1498–1500 (2011)
Taur, Y., Liang, X., Wang, W., Lu, H.: A continuous, analytic drain current model for DG MOSFETs. IEEE Electron Device Lett. 25, 107–110 (2004)
Chen, Q., Harrell, E., Meindl, J.: A physical short channel threshold voltage model for undoped symmetric double gate MOSFETs. IEEE Trans. Electron Devices 50, 1631–1638 (2003)
Liang, X., Taur, Y.: A 2-D analytical solution for SCEs in DGMOSFETs. IEEE Trans. Electron Devices 51, 1385–1392 (2004)
Suzuki, K., Tanaka, T., Tosaka, Y., Horie, H., Arimoto, Y.: Scaling theory for double-gate SOI MOSFETs. IEEE Trans. Electron Devices 40, 2326–2330 (1993)
Liu, L., Mohata, D., Datta, S.: Scaling length theory of double-gate interband tunnel field-effect transistors. IEEE Trans. Electron Devices 57, 827–835 (2012)
Pan, A., Chui, C.: A quasi-analytical model for double-gate tunneling field-effect transistors. IEEE Electron Device Lett. 33, 1468–1471 (2012)
Liu, Z., Hu, C., Huang, J., Chan, T., Jeng, M., Ko, P., Cheng, Y.: Threshold voltage model for deep-submicrometer MOSFETs. IEEE Trans. Electron Devices 40, 86–96 (1993)
Ionescu, A., Riel, H.: Tunnel field-effect transistors as energy-efficient electronic switches. Nature 479, 329–338 (2011)
Boucart, K., Ionescu, A.: Threshold voltage in tunnel FETs: physical definition, extraction, scaling and impact on IC design. In: 37th ESSDERC, pp. 299–302 (2007)
Bardon, M., Neves, H., Puers, R., Hoof, C.: Pseudo-two-dimensional model for double-gate tunnel FETs considering the junctions depletion regions. IEEE Trans. Electron Devices 57, 827–835 (2010)
Booth, R., White, M., Wong, H., Krutsick, T.: The effect of channel implants on MOS transistor characterization. IEEE Trans. Electron Devices ED 34, 2501–2510 (1987)
Chander, S., Baishya, S.: A two-dimensional gate threshold voltage model for a heterojunction SOI-tunnel FET with oxide/source overlap. IEEE Electron Device Lett. 36, 714–717 (2015)
Maity, N., Maity, R., Thapa, R., Baishya, S.: Study of interface charge densities for ZrO2 and HfO2 based metal–oxide–semiconductor devices. Adv. Mater. Sci. Eng. 2014, 1–6 (2014)