An Efficient Wavelet Based Transient Current Test towards Detection of Data Retention Faults in SRAM
Tóm tắt
Advancements in integrated circuit technologies, increasing manufacturing complexity and incessant device scaling inflict new challenges in memory testing and demand for new, sophisticated test methods. Much research has been devoted to reducing the test time of Data Retention Fault (DRF) using March tests. Recent advancements in research rely on using transient current based tests for fault detection. As the test length of a transient current test is comparatively small when compared to other test methods, the probability of detection of this kind of fault during a test period is very low especially in the case of small memory arrays. Large variations in peak amplitude of voltage and charge may occur due to process variations which limits the detection capability of such tests. The main contribution of this paper is enhancing the detection of DRFs in SRAM using transient current test amidst process variations. In this paper, we implement an innovative approach to SRAM test - wavelet based transient supply current test with modified March sequence exploiting Read Equivalent Stress (RES) for DRF detection. The proposed technique can be merged with transient current test using Built-in-Current Sensors (BICS) resulting in full coverage of DRF. In comparison with other techniques that solely rely on software implementation for fault detection, the proposed technique significantly reduces hardware and performance penalties. Simulation results confirm that compared to other methods the proposed technique can provide high standards of reliability and efficiency in DRF detection.
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