An Automatic Method of Mapping I/O Sequences of Chip Execution onto High-level Design for Post-Silicon Debugging

[1] AMBA interface specifications: http://www.arm.com/products/system-ip/amba/

[2] M. Abramovici, P. Bradley, K.r Dwarakanath, P. Levin, G. Memmi, and D. Miller, “A reconfigurable design-for-debug infrastructure for SoCs,” Proc. Design Automation Conference, pp.7-12, 2006.

[3] N. Bombieri, N. Deganello, and F. Fummi, “Integrating RTL IPs into TLM designs through automatic transactor generation,” Proc. Design, Automation and Test in Europe, pp.15-20, 2008.

[4] Collett ASIC/IC Verification Study, 2004 (data for 180nm and 130nm).

10.1145/77606.77608

[6] Y. Ishikawa, S. Watanabe, K. Seto, and M. Fujita, “Protocol wrapper generation from statement based specification,” Proc. International Workshop on Logic and Synthesis 2006, pp.118-125, June 2006.

[7] H.G. Ko and N. Nicolici, “Automated trace signals identification and state restoration for improving observability in post-silicon validation,” Proc. Design, Automation, and Test in Europe, pp.1298-1303, 2008.

[8] A. Koelbl, Y. Lu, and A. Mathur, “Embedded tutorial: Formal equivalence checking between system-level models and RTL,” Proc. International Conference on Computer-Aided Design, pp.965-971, Nov. 2005.

[9] Y. Lee, T. Nishihara, T. Matsumoto, and M. Fujita, “A post-silicon debug support using high-level design description,” Proc. 18th Asian Test Symposium, pp.141-147, Nov. 2009.

[10] MIPS Technologies Inc., EJTAG Trace Control Block Specification. http://www.mips.com

[11] NEXUS 5001™ Forum: http://www.nexus5001.org/

[12] P. Cahuhan, D. Goyal, G. Hasteer, A. Mathur, and N. Sharma, “Non-cycle-accurate Sequential Equivalence Checking,” Proc. Design Automation Conference, pp.460-465, July 2009.

[13] D.D. Gajski, J. Zhu, R. Doemer, A. Gerstlauer, and S. Zhao, SpecC: Specification Language and Methodology, Kluwer Academic, 2000.

[14] R. Ulrich, W. Grafen, J. Haufe, and J. Grosse, “Debugging of FPGA based prototypes — A case study,” Proc. of Design, Automation and Test in Europe Conference, Designer's Forum, pp.109-113, 2001.

[15] S. Watanabe, K. Seto, Y. Ishikawa, S. Komatsu, and M. Fujita, “Protocol transducer synthesis using divide and conquer approach,” Proc. 12th Asia and South Pacific Design Automation Conference, pp.280-285, Jan. 2007.

[16] J. Yang and N.A. Touba, “Expanding trace buffer observation window for in-system debug through selective capture,” Proc. VLSI Test Symposium, pp.345-351, 2008.

[17] A. Zeller, Why Programs Fail: A Guide to Systematic Debugging, Morgan Kaufmann, 2005.