Adaptive cluster growth: a new algorithm for circuit placement in rectilinear regions

Computer-Aided Design - Tập 24 - Trang 27-35 - 1992
C-M. Kyung1, J. Widder2, D.A. Mlynski2
1Department of Electrical Engineering, Korea Advanced Institute of Science and Technology, PO Box 150, Cheongryang, Seoul, South Korea
2Institut für Theoretische Elektrotechnik und Messtechnik, Universität Karlsruhe, Karlsruhe, Germany

Tài liệu tham khảo

Sahni, 1980, The complexity of design automation problems, 420 Donath, 1980, Complexity theory and design automation, 412 Breuer, 1977, Min-cut placement, J. Des. Automat. & Fault Tolerant Comput., Vol 1, 343 Dunlop, 1985, A procedure for placement of standard-cell VLSI circuits, IEEE Trans. CAD Integr. Circuits & Syst., Vol CAD-4, 92, 10.1109/TCAD.1985.1270101 Kernighan, 1970, An effective heuristic for partitioning graphs, BST J., Vol. 49, 291 Fiduccia, 1982, A linear-time heuristic for improving network partitions, 175 Chi, 1987, An automatic rectilinear partitioning procedure for standard cells, 50 Ohtsuki, 1982, Minimum dissection of rectilinear region, 1210 Quinn, 1979, A force-directed component placement procedure for printed circuit boards, IEEE Trans. Circuits & Syst., Vol CAS, 377, 10.1109/TCS.1979.1084652 Cheng, 1984, Module placement based on resistive network optimization, IEEE Trans. CAD Integr. Circuits & Syst., Vol CAD-3, 218, 10.1109/TCAD.1984.1270078 Tsay, 1988, Module placement for large chips based on sparse linear equations, Int. J. Circuit Theory & Applic., Vol 16, 416, 10.1002/cta.4490160406 Blanks, 1988, Near-optimal placement using a quadratic objective function, 609 Frankle, 1986, Circuit placement and cost bound by eigenvector decomposition, 414 Kleinhans, 1988, GORDIAN: a new global optimization/rectangle dissection method for cell placement, 506 Wipfler, 1982, A combined force and cut algorithm for hierarchical VLSI layout, 671 Just, 1986, On the relative placement and the transportation problem for standard-cell layout, 308 Sha, 1985, An analytical algorithm for placement of arbitrary sized rectangular blocks, 602 Dai, 1986, Hierarchical floor planning for building block layout, 454 Suaris, 1989, A quadrisection-based combined place and route scheme for standard cells, IEEE Trans. Integr. Circuits & Syst., Vol CAD-8, 234, 10.1109/43.21843 La, 1986, Mason: a global floorplanning approach for VLSI design, IEEE Trans. Integr. Circuits & Syst., Vol CAD-5, 477 Wong, 1986, A new algorithm for floorplan design, 101 Maling, 1982, On finding most optimal rectangular package plans, 663 Kirkpatrick, 1983, Optimization by simulated annealing, Science, Vol 220, 671, 10.1126/science.220.4598.671 Sechen, 1986, Timber Wolf 3.2: a new standard cell placement and global routing package, 432 Shin, 1986, Two-dimensional compaction by zone refining, 115 Park, I C and Kyung, C M ‘Circuit placement in rectilinear region using graph matching’ (in preparation) Preas, 1987, Benchmarks for cell-based layout systems, 319