Adaptive Debug and Diagnosis Without Fault Dictionaries

Springer Science and Business Media LLC - Tập 25 Số 4-5 - Trang 259-268 - 2009
Stefan Holst1, Hans-Joachim Wunderlich2
1Institut für Technische Informatik, Universität Stuttgart, Stuttgart, Germany 70569#TAB#
2Institut für Technische Informatik, Universität Stuttgart, Stuttgart, Germany

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Tài liệu tham khảo

Abramovici M, Breuer MA (1980) Fault diagnosis based on effect-cause analysis: an introduction. In: 17th conference on design automation, pp 69–76

Amyeen ME, Nayak D, Venkataraman S (2006) Improving precision using mixed-level fault diagnosis. In: Proceedings IEEE international test conference 2006, Santa Clara, 24–26 October 2006, p 22.3

Arnaout T, Bartsch G, Wunderlich H-J (2006) Some common aspects of design validation, debug and diagnosis. In: Third IEEE international workshop on electronic design, test and applications (DELTA 2006), Kuala Lumpur, 17–19 January 2006, pp 3–10

Bartenstein T (2000) Fault distinguishing pattern generation. In: Proceedings IEEE international test conference 2000, Atlantic City, pp 820–828

Bartenstein T, Heaberlin D, Huisman LM, Sliwinski D (2001) Diagnosing combinational logic designs using the single location at-a-time (SLAT) paradigm. In: Proceedings IEEE international test conference 2001, Baltimore, 30 October–1 November 2001, pp 287–296

Bhatti NK, Blanton RS (2006) Diagnostic test generation for arbitrary faults. In: Proceedings IEEE international test conference 2006, Santa Clara, 24–26 October, 2006, p 19.2

Boppana V, Fujita M (1998) Modeling the unknown! towards model-independent fault and error diagnosis. In: Proceedings IEEE international test conference 1998, Washington, DC, 18–22 October 1998, pp 1094–1100

Boppana V, Hartanto I, Fuchs WK (1996) Full fault dictionary storage based on labeled tree encoding. In: 14th IEEE VLSI test symposium (VTS’96), Princeton, 28 April–1 May 1996, pp 174–179

Chen KC (2003) Assertion-based verification for SoC designs. In: Proceedings 5th international conference on ASIC, vol 1, pp 12–15

Chess B, Larrabee T (1999) Creating small fault dictionaries. IEEE Trans Comput-aided Des Integr Circuits Syst 18(3):346–356

Chess B, Lavo DB, Ferguson FJ, Larrabee T (1995) Diagnosis of realistic bridging faults with single stuck-at information. In: Proceedings of the 1995 IEEE/ACM international conference on computer-aided design, 1995, San Jose, 5–9 November 1995, pp 185–192

Desineni R, Poku O, Blanton RDS (2006) A logic diagnosis methodology for improved localization and extraction of accurate defect behavior. In: Proceedings IEEE international test conference 2006, Santa Clara, 24–26 October 2006, p 12.3

Fan X, Moore W, Hora C, Gronthoud G (2005) Stuck-open fault diagnosis with stuck-at model. In: Proceedings European test symposium, Tallin, pp 182–187

Fitzpatrick T (2005) Realizing advanced functional verification with questa. Mentor Graphics Corporation (white paper)

Gong Y, Chakravarty S (1995) On adaptive diagnostic test generation. In: Proceedings IEEE international conference on computer-aided design, p 181

Henderson CL, Soden JM (1997) Signature analysis for ic diagnosis and failure analysis. In: Proceedings IEEE international test conference 1997, Washington, DC, 3–5 November 1997, pp 310–318

Holst S, Wunderlich H-J (2007) Adaptive debug and diagnosis without fault dictionaries. In: 12th European test symposium (ETS 2007), 20 May 2007, Freiburg, pp 7–12

Hora C, Segers R, Eichenberger S, Lousberg M (2002) An effective diagnosis method to support yield improvement. In: Proceedings IEEE international test conference 2002, Baltimore, 7–10 October 2002, pp 260–269

Huisman LM (2004) Diagnosing arbitrary defects in logic designs using single location at a time (SLAT). IEEE Trans Comput-aided Des Integr Circuits Syst 23(1):91–101

Klein R, Piekarz T (2005) Accelerating functional simulation for processor based designs. Mentor Graphics Corporation (white paper)

Krstic A, Wang L-C, Cheng K-T, Liou J-J, Abadir MS (2003) Delay defect diagnosis based upon statistical timing models—the first step. In: 2003 design, automation and test in Europe conference and exposition (DATE 2003), Munich, 3–7 March 2003, pp 10328–10335

Lavo DB, Chess B, Larrabee T, Hartanto I (1998) Probabilistic mixed-model fault diagnosis. In: Proceedings IEEE international test conference 1998, Washington, DC, 18–22 October 1998, pp 1084–1093

McPherson JW (2006) Reliability challenges for 45nm and beyond. In: Proceedings of the 43rd design automation conference, DAC 2006, San Francisco, 24–28 July 2006, pp 176–181

Millman SD, McCluskey EJ, Acken JM (1990) Diagnosing CMOS bridging faults with stuck-at fault dictionaries. In: Proceedings IEEE international test conference, pp 860–870

Pomeranz I, Reddy SM (1992) On the generation of small dictionaries for fault location. In: IEEE/ACM international conference on computer-aided design, ICCAD92, Santa Clara, 8–12 November 1992, pp 272–279

Renovell M, Huc P, Bertrand Y (1994) CMOS bridging fault modeling. In: 12th IEEE VLSI test symposium (VTS), 25–28 Apr 1994, pp 392–297

Riley M, Chelstrom N, Genden M, Sawamura S (2006) Debug of the CELL processor: moving the lab into silicon. In: Proceedings IEEE international test conference 2006, Santa Clara, 24–26 October 2006, p 26.1

Roy K, Mak TM, Cheng K-TT (2006) Test consideration for nanometer-scale cmos circuits. IEEE Des Test Comput 23(2):128–136

Ubar R (2003) Design error diagnosis with resynthesis in combinational circuits. J Electron Test Theory Appl 19:73–82

Veneris AG, Chang R, Abadir MS, Amiri M (2004) Fault equivalence and diagnostic test generation using atpg. In: Proceedings IEEE international symposium on circuits and systems, 2004, pp 221–224

Waicukauski JA, Lindbloom E (1989) Failure diagnosis of structured VLSI. IEEE Des Test Comput 6(4):49–60

Wunderlich H-J (2005) From embedded test to embedded diagnosis. In: Proceedings European test symposium, Tallin, pp 216–221