A scheduler synthesis methodology for joint SW/HW design exploration of SoC
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Dutta S, Jensen R, Rieckmann A (2001) Viper: A multiprocessor SOC for advanced set-top box and digital TV systems. IEEE Des Test Comput 18(5):21–31
Stravers P, Hoogerbrugge J (2001) Homogeneous multiprocessing and the future of silicon design paradigms. In: International symposium on VLSI technology, systems, and applications (VLSI-TAS), pp 184–187
Adiletta M, Rosenbluth M, Bernstein D, Wolrich G, Wilkinson H (2002) The next generation of Intel IXP network processors. In: INTEL Technology Journal, vol 6, Intel Communications Group, Intel Corporation, Aug 2002
Moonen A, van den Berg R, Bekooij M, Bhullar H, van Meerbergen J (2005) A multi-core architecture for in-car digital entertainment. In: Proceedings of the GSPx conference
Clements PC, Northrop L (2001) Software product lines: Practices and patterns. Addison-Wesley, Reading
Meyer MH, Lehnerd AP (1997) The power of product platforms: building value and cost leadership. Free Press, New York
Paulin PG, Pilkington C, Langevin M, Bensoudane E, Nicolescu G (2004) Parallel programming models for a multi-processor soc platform applied to high-speed traffic management. In: CODES+ISSS ’04: Proceedings of the 2nd IEEE/ACM/IFIP international conference on hardware/software codesign and system synthesis. ACM Press, New York, pp 48–53
Cornea R, Dutt N, Gupta R, Krueger I, Nicolau A, Schmidt D, Shukla S (2003) Forge: A framework for optimization of distributed embedded systems software. In: IPDPS ’03: Proceedings of the 17th international symposium on parallel and distributed processing. IEEE Computer Society, Washington, p 208.1
Cesario W, Baghdadi A, Gauthier L, Lyonnard D, Nicolescu G, Paviot Y, Yoo S, Jerraya AA, Diaz-Nava M (2002) Component-based design approach for multicore socs. In: DAC ’02: Proceedings of the 39th conference on design automation. ACM Press, New York, pp 789–794
Jalabert A, Murali S, Benini L, Micheli GD (2004) Pipescompiler: A tool for instantiating application specific networks on chip. In: DATE, pp 884–889
Sangiovanni-Vincentelli A (2002) Defining platform-based design. EEdesign, EETimes
Balarin F, Watanabe Y, Hsieh H, Lavagno L, Passerone C, Sangiovanni-Vincentelli A (2003) Metropolis: An integrated electronic system design environment. Computer 36(4):45–52
Theelen BD, Florescu O, Geilen M, Huang J, van der Putten PHA, Voeten J (2007) Software/hardware engineering with the parallel object-oriented specification language. In: 5th ACM & IEEE international conference on formal methods and models for co-design (MEMOCODE 2007), May 30–June 1st, Nice, France, 2007, pp 139–148
Tibboel W, Reyes V, Klompstra M, Alders D (2007) System-level design flow based on a functional reference for hw and sw. In: DAC ’07: Proceedings of the 44th annual conference on design automation. ACM Press, New York, pp 23–28
van der Wolf P, de Kock E, Henriksson T, Kruijtzer W, Essink G (2004) Design and programming of embedded multiprocessors: an interface-centric approach. In: CODES+ISSS ’04: Proceedings of the 2nd IEEE/ACM/IFIP international conference on hardware/software codesign and system synthesis. ACM Press, New York, pp 206–217
Reyes V, Kruijtzer W, Bautista T, Alkadi G, Nún̈ez A (2006) A unified system-level modeling and simulation environment for mpsoc design: Mpeg-4 decoder case study. In: DATE ’06: Proceedings of the conference on design, automation and test in Europe, 3001 Leuven, Belgium, Belgium: European Design and Automation Association, pp 474–479
Thiele L, Chakraborty S, Gries M, Kinzli S (2002) Design space exploration of network processor architectures. HPCA Workshop, February 2002
Gries M, Kulkarni C, Sauer C, Keutzer K (2003) Comparing analytical modeling with simulation for network processors: A case study. In: DATE
Goossens K, Dielissen J, Gangwal OP, González Pestana S, Rădulescu A, Rijpkema E (2005) A design flow for application-specific networks on chip with guaranteed performance to accelerate SOC design and verification. In: DATE’05. IEEE CS, Washington, pp 1182–1187
Kumar A, Hansson A, Huisken J, Corporaal H (2007) Interactive presentation: an fpga design flow for reconfigurable network-based multi-processor systems on chip. In: DATE ’07: Proceedings of the conference on design, automation and test in Europe. ACM Press, New York, pp 117–122
Assayad I, Bertin V, Defaut F-X, Gerner P, Quévreux O, Yovine S (2005) Jahuel: A formal framework for software synthesis. In: ICFEM’05
Assayad I, Yovine S (2006) System platform simulation model applied to multiprocessor video encoding. In: IEEE symposium on industrial embedded systems
Assayad I, Yovine S (2007) P-Ware: A precise and scalable component-based simulation tool for embedded multiprocessor industrial applications. In: EUROMICRO DSD
Assayad I, Yovine S (2005) Compositional constraints generation for concurrent real time loops with interdependent iterations. In: I2CS’05. LNCS. Springer, Berlin
Assayad I, Yovine S (2007) Modelling and exploration environment for application specific multiprocessor systems. In: HASE ’07. IEEE CS, Washington, pp 433–434
Assayad I, Gerner P, Yovine S, Bertin V (2005) Modelling, analysis and implementation of an on-line video encoder. In: DFMA’05. IEEE Computer Society, Washington
Requirements for ip version 4 routers, United States, June 1995
IXP2800, Network processor hardware reference manual, http://www.intel.com/design/network/manuals/278882.htm
