A scalable LDPC decoder ASIC architecture with bit-serial message exchange

Gallager, 1962, Low-density parity-check codes, IRE Trans. Inform. Theory, IT-8, 21, 10.1109/TIT.1962.1057683 DVB-S2 White Paper 〈http://www.dvb.org/documents/white-papers/wp06.DVB-S2.final.pdf〉. IEEE Standard 802.16 (WirelessMAN), 〈www.ieee802.org/16/〉. IEEE Standard 802.3 (CSMA/CD) 〈www.ieee802.org/3/〉. P. Urard, E. Yeo, L. Paumier, P. Georgelin, T. Michel, V. Lebars, E. Lantreibecq, B. Gupta, A 135Mb/s DVB-S2 Compliant CODEC Based on 64,800b LDPC and BCH Codes, 2005 IEEE ISSCC Digest of Technical Papers, February 2005. Blanksby, 2002, A 690-mW 1-Gb/s 1024-b, rate-1/2 low-density parity-check decoder, IEEE J. Solid-State Circuits, 37, 404, 10.1109/4.987093 A. Darabiha, A. Chan Carusone, F. Kschischang, Multi-Gbit/sec low-density parity-check decoders with reduced interconnect complexity, in: IEEE International Symposium on Circuits and Systems, May 2005, pp. 5194–5197. E. Boutillon, J. Castura, F. Kschischang, Decoder-first code design, in: Second International Symposium on Turbo Codes and Related Topics, Brest, France, September 2000, pp. 459–462. Yeo, 2003, Iterative decoder architectures, IEEE Commun. Mag., 41, 132, 10.1109/MCOM.2003.1222729 E. Liao, E. Yeo, B. Nikolić, Low-density parity-check code constructions for hardware implementation, in: IEEE International Conference on Communications, Paris, France, June 2004. pp. 2573–2577 Mansour, 2003, High-throughput LDPC decoders, IEEE Trans. VLSI Syst., 11, 976, 10.1109/TVLSI.2003.817545 Mansour, 2006, A 640-Mb/s 2048-bit programmable LDPC decoder chip, IEEE J. Solid-State Circuits, 41, 684, 10.1109/JSSC.2005.864133 Chen, 2005, Reduced-complexity decoding of LDPC codes, IEEE Trans. Commun., 53, 1288, 10.1109/TCOMM.2005.852852 Zhang, 2004, Joint (3,k)-regular LDPC code and decoder/encoder design, IEEE Trans. Signal Process., 52, 1065, 10.1109/TSP.2004.823508 Lin, 2004 Kschischang, 2001, Factor graphs and the sum–product algorithm, IEEE Trans. Inform. Theory, 47, 498, 10.1109/18.910572 Schlegel, 2004 S. Howard, C. Schlegel, V. Gaudet, A degree-matched check node approximation for LDPC decoding, in: IEEE International Symposium on Information Theory, September 2005, pp. 1131–1135. Berrou, 1993, Near Shannon limit error-correcting coding and decoding: turbo-codes, IEEE Int. Conf. Commun., 2, 1064 Winstead, 2004, CMOS analog MAP decoder for (8,4) Hamming code, IEEE J. Solid-State Circuits, 39, 122, 10.1109/JSSC.2003.820845 Gaudet, 2003, A 13.3-Mb/s 0.35μm CMOS analog turbo decoder IC with a configurable interleaver, IEEE J. Solid-State Circuits, 38, 2010, 10.1109/JSSC.2003.818134 S. Hemati, A. Banihashemi, C. Plett, An 80-Mb/s 0.18μm CMOS analog min-sum iterative decoder for a (32,8,10) LDPC Code, in: IEEE Custom Integrated Circuits Conference, September 2005, pp. 240–243. Vogrig, 2005, A 0.35μm CMOS analog turbo decoder for the 40-bit rate 1/3 UMTS channel code, IEEE J. Solid-State Circuits, 40, 753, 10.1109/JSSC.2005.843628 M. Moerz, T. Gabara, R. Yan, J. Hagenauer, An analog 0.25μm BiCMOS Tailbiting MAP decoder, in: IEEE International Solid-State Circuits Conference, February 2000, pp. 356–357. F. Lustenberger, M. Helfenstein, G. Moschytz, H.-A. Loeliger, F. Tarkoy, All-analog decoder for a binary (18,9,5) Tail-Biting Trellis Code, in: European Solid-State Circuits Conference, September 1999, pp. 362–365. Arzel, 2005, Analog slice turbo decoding, IEEE Int. Symp. Circuits Syst., 1, 332, 10.1109/ISCAS.2005.1464592 IEEE Standard 802.11 (Wireless LAN), 〈www.ieee802.org/11/〉. V. Gaudet, B. Cockburn, C. Schlegel, S. Bates, P. Goud, R. Hang, A. Rapley, S. Howard, Method and Apparatus for Digit-Serial Communications for Iterative Digital Processing Algorithms, provisional US pat. applic. no. 60/570,901 filed May 14, 2004; PTO filed May 13, 2005. Parhi, 1991, A systematic approach for design of digit-serial signal processing architectures, IEEE Trans. Circuits Syst., 38, 358, 10.1109/31.75394 Bree, 1992, A modular bit-serial architecture for large-constraint-length Viterbi decoding, IEEE J. Solid-State Circuits, 27, 184, 10.1109/4.127341 H. Suzuki, Y.-N. Chang, K. Parhi, Low-power bit-serial Viterbi decoder for 3rd generation W-CDMA systems, in: IEEE Custom Integrated Circuits Conference, May 1999, pp. 589–592. Parhi, 2004, An improved pipelined MSB-first add-compare select unit structure for Viterbi decoders, IEEE Trans. Circuits Syst. I: Regular Papers, 51, 504, 10.1109/TCSI.2004.823657 A. Darabiha, A. Carusone, F. Kshischang, A bit-serial approximate min-sum LDPC decoder and FPGA implementation, in: IEEE International Symposium on Circuits and Systems, Kos, Greece, May 2006. Hu, 2001, Progressive edge-growth tanner graphs, IEEE Global Telecommun. Conf. (GLOBECOM), 2, 995, 10.1109/GLOCOM.2001.965567