A multiple-valued logic approach to the design and verification of hardware circuits

Journal of Applied Logic - Tập 15 - Trang 69-93 - 2016
Amnon Rosenmann1
1Institute of Discrete Mathematics, Graz University of Technology, Steyrergasse 30, A-8010 Graz, Austria

Tài liệu tham khảo

Banks, 2010 Bergmann, 2008 Bertacco, 2006 Biere, 1999, Symbolic model checking without BDDs, 193 Bochvar, 1981, On a three-valued logical calculus and its application to the analysis of the paradoxes of the classical extended functional calculus, Hist. Philos. Logic, 2, 87, 10.1080/01445348108837023 Brayton, 1984 Cerný, 2012, Simulation distances, Theor. Comput. Sci., 413, 21, 10.1016/j.tcs.2011.08.002 Chang, 1958, Algebraic analysis of many valued logics, Trans. Am. Math. Soc., 88, 467, 10.1090/S0002-9947-1958-0094302-9 Chang, 1959, A new proof of the completeness of the Łukasiewicz axioms, Trans. Am. Math. Soc., 93, 74 Clarke, 2001 de Moura, 2003, Bounded model checking and induction: from refutation to verification, 14 Dhande, 2007, Ternary logic simulator using VHDL Dubrova, 2002, Multiple-valued logic synthesis and optimization, 89 Gottwald, 2001, A Treatise on Many-Valued Logics, vol. 9 Hunter, 2013, Expressive completeness for metric temporal logic, 349 IEEE1164, IEEE Standard Multivalue Logic System for VHDL Model Interoperability (Stdlogic1164), IEEE Std 1164-1993 (1993). IEEE1364, IEEE Standard Hardware Description Language Based on the Verilog(R) Hardware Description Language, IEEE Std 1364-1995 (1996) 1–688. Karfa, 2010 Kleene, 1938, On a notation for ordinal numbers, J. Symb. Log., 3, 150, 10.2307/2267778 Koymans, 1990, Specifying real-time properties with metric temporal logic, Real-Time Syst., 2, 255, 10.1007/BF01995674 Krishnaswamy, 2009, Signature-based SER analysis and design of logic circuits, IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst., 28, 74, 10.1109/TCAD.2008.2009139 Lam, 2005 Łukasiewicz, 1967, Philosophical remarks on many-valued systems of propositional logic McCluskey, 1956, Minimization of Boolean functions, Bell Syst. Tech. J., 35, 1417, 10.1002/j.1538-7305.1956.tb03835.x McMillan, 2003, Interpolation and SAT-based model checking, vol. 2725, 1 Miller, 2008, Multiple Valued Logic – Concepts and Representations, vol. 12 Molitor, 2004 Novák, 1999 O'Donnell, 2014 Plaza, 2005 Quine, 1952, The problem of simplifying truth functions, Am. Math. Mon., 59, 521, 10.1080/00029890.1952.11988183 Rosenmann, 2002, Alignability equivalence of synchronous sequential circuits, 111 Rozon, 1996, On the use of VHDL as a multi-valued logic simulator, 110 R.L. Rudell, Multiple-valued logic minimization for PLA synthesis, Berkeley, 1986, Memorandum No. UCB/ERL M86-65. Seger, 1995, Formal verification by symbolic evaluation of partially-ordered trajectories, Form. Methods Syst. Des., 6, 147, 10.1007/BF01383966 Sheeran, 2000, Checking safety properties using induction and a SAT-solver, 108 Wegener, 1987, The Complexity of Boolean Functions Wilson, 2000, Reliable verification using symbolic simulation with scalar values, 124 Wilson, 2000, Symbolic simulation with approximate values, 470 Xie, 2011, HDL-mutation based simulation data generation by propagation guided search, 608 Zadeh, 1965, Fuzzy sets, Inf. Control, 8, 338, 10.1016/S0019-9958(65)90241-X Zadeh, 1996, Fuzzy Sets, Fuzzy Logic, and Fuzzy Systems, vol. 6