A methodology for speeding up matrix vector multiplication for single/multi-core architectures

Vasilios Kelefouras1, Angeliki Kritikakou2, Elissavet Papadima1, C.E. Goutis1
1Department of Electrical and Computer Engineering, University of Patras, Patras, Greece
2Education and Research Department in Computer science and Electrical Engineering, University of Rennes 1-IRISA/INRIA, Rennes, France

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