A low quiescent current power-on-reset circuit with configurable trip voltage
Tài liệu tham khảo
Hirata A, Nakanishi K, Nozoe M, Miyoshi A. The cross charge-control flip-flop: a low-power and high-speed flip-flop suitable for mobile application SoCs. In: Digest of Technical Papers. 2005 Symposium on VLSI Circuits; 2005. p. 306–307. doi: 10.1109/VLSIC.2005.1469392.
Rahiminejad, 2014, Low-power pulsed hybrid flip-flop based on a C-element, AEU - Int J Electron Commun, 68, 907, 10.1016/j.aeue.2014.04.012
Moreau L, Dekimpe R, Bol D. A 0.4V 0.5fJ/cycle TSPC flip-flop in 65nm LP cmos with retention mode controlled by clock-gating cells. In: 2019 IEEE International Symposium on Circuits and Systems (ISCAS); 2019. p. 1–4. doi:https://doi.org/10.1109/ISCAS.2019.8702680.
Khateb, 2019, Multiple-input bulk-driven quasi-floating-gate MOS transistor for low-voltage low-power integrated circuits, AEU - Int J Electron Commun, 100, 32, 10.1016/j.aeue.2018.12.023
Cerqueira, 2020, Catena: A near-threshold, Sub-0.4-mW, 16-Core programmable spatial array accelerator for the ultralow-power mobile and embedded internet of things, IEEE J Solid-State Circ, 55, 2270, 10.1109/JSSC.2020.2978137
Ryu, 2021, Variation-tolerant elastic clock scheme for low-voltage operations, IEEE J Solid-State Circ, 56, 2245, 10.1109/JSSC.2020.3048881
Rezaei, 2021, An efficient high speed and low power voltage-level shifter, AEU - Int J Electron Commun, 138, 153857, 10.1016/j.aeue.2021.153857
Chi, 2007, Gate level multiple supply voltage assignment algorithm for power optimization under timing constraint, IEEE Trans Very Large Scale Integr VLSI Syst, 15, 637, 10.1109/TVLSI.2007.898650
Myers, 2016, A subthreshold ARM Cortex-M0+ subsystem in 65 nm CMOS for WSN applications with 14 power domains, 10T SRAM, and integrated voltage regulator, IEEE J Solid-State Circ, 51, 31, 10.1109/JSSC.2015.2477046
Jeong, 2021, A wide-range static current-free current mirror-based LS with logic error detection for near-threshold operation, IEEE J Solid-State Circ, 56, 554, 10.1109/JSSC.2020.3014954
Volkan K, Friedman EG. Supply and Threshold Voltage Scaling Techniques, John Wiley & Sons, Ltd; 2006, Ch. 3. p. 45–84. doi:https://doi.org/10.1002/0470033371.ch3.
Pandey P. Low-voltage power-on-reset circuit with least delay and high accuracy. Electron Lett 2015;51: 856–58(2). doi:https://doi.org/10.1049/el.2014.4203.
Le, 2011, A long reset-time power-on reset circuit with brown-out detection capability, IEEE Trans Circ Syst II Exp Briefs, 58, 778
Bo Zhou, 2016, Low-complexity 0.55V 2.5μW bandgap reference and power-on reset hybrid circuit, Electron Lett, 52
Zhou, 2020, Sub-1-V BGR and POR hybrid circuit with 2.25μA current dissipation and low complexity, IEEE Trans Very Large Scale Integr VLSI Syst, 28, 2228, 10.1109/TVLSI.2020.3009452
Feldman, 2020, An accurate 0.55V 2.6μW voltage-level detector, IEEE Solid-State Circ Lett 3, 166, 10.1109/LSSC.2020.3005792
Y. Lin, K. Xu, A temperature-compensated power-on-reset circuit in 40nm CMOS, in: 2019 IEEE International Conference on Electron Devices and Solid-State Circuits (EDSSC), 2019, pp. 1–2. doi:https://doi.org/10.1109/EDSSC.2019.8754457.
Guo, 2021, An ultra-low quiescent current resistor-less power on reset circuit, IEEE Trans Circ Syst II Exp Briefs, 68, 146
Amaya A, Rueda LEG, Roa E. A multi-level power-on reset for fine-grained power management. In: 2018 28th International Symposium on Power and Timing Modeling, Optimization and Simulation (PATMOS); 2018. p. 129–132. doi:https://doi.org/10.1109/PATMOS.2018.8464167.
Seok, 2012, A portable 2-transistor picowatt temperature-compensated voltage reference operating at 0.5 V, IEEE J Solid-State Circ, 47, 2534, 10.1109/JSSC.2012.2206683