A framework for solving VLSI graph layout problems

Bentley, 1979, A tree machine for searching problems

Bhatt, 1982

Bhatt, 1982, Minimizing the Longest Edge in a VLSI Layout, MIT VLSI Memo 82–86

Bhatt, 1982, How to assemble tree machines,

Bilardi, 1981, A critique and appraisal of VLSI models of computation

Breuer, 1977, Min-cut placement, J. Design Automation and Fault Tolerant Computing, 1, 343

But, 1983, On Bisecting Random Graphs

Cappello, 1981, Area-Efficient VLSI Structures for Multiplying at Clock Rate

Dolev, 1983, Planar embeddings of planar graphs, MIT LCS Technical Memo 237

Fiduccia, 1982

Floyd, 1980, The compilation of regular expressions into integrated circuits

Gabber, 1979, Explicit constructions of linear size superconcentrators, 364

Garey, 1979

M. R. Garey and D. S. Johnson, unpublished manuscript, 1982.

Gilbert, 1980, Graph Separator Theorems and Sparse Gaussian Elimination

Goldberg, 1982

Greene, 1983, Area and delay penalties in restructurable wafer-scale arrays

Kernighan, 1970, An efficient heuristic procedure for partitioning graphs, Bell System Tech. J., 291, 10.1002/j.1538-7305.1970.tb01770.x

Leighton, 1981, Layouts for the Shuffle-Exchange Graph and Lower Bound Techniques for VLSI

Leighton, 1983, Complexity Issues in VLSI

Leighton, 1981, New lower bound techniques for VLSI

Leighton, 1982, A layout strategy for VLSI which is provably good

Leighton, 1982, Wafer-scale integration of systolic arrays

Leighton, 1982, Three Dimensional Circuit Layouts, M.I.T. VLSI Memo 102

Leiserson, 1979, A Model for VLSI Computations

Leiserson, 1979, Systolic priority queues

Leiserson, 1980, Area-efficient layouts (for VLSI)

Leiserson, 1983, Area-Efficient VLSI Computation

Lewis, 1965, Memory bounds for recognition of context-free and context-sensitive languages

Lipton, 1977, A separator theorem for planar graphs

Magó, 1979, A network of microprocessors to execute reduction languages. I and II, Internat. J. Comput. Inform. Sci.

Mead, 1980

K. Mehlhorn, personal communication, 1982.

Nath, 1983, Efficient VLSI networks for parallel processing based on orthogonal trees, IEEE Trans. Comput., 10.1109/TC.1983.1676279

Paterson, 1981, Bounds on minimax edge for complete binary trees

Raffel, 1979, On the use of nonvolatile programmable links for restructurable VLSI

Ramachandran, 1982, On driving many long lines in a VLSI layout

Rivest, 1982, The “PI” (placement and interconnect) system

Rosenberg, 1981, Routing with Permuters: Toward Reconfigurable and Fault-Tolerant Networks

Ruzzo, 1981, Minimum edge length planar embeddings of trees

Sangiovanni-Vincentelli, 1977, An efficient heuristic cluster algorithm for tearing large-scale networks, IEEE Trans. Circuits Systems, CAS-24, 709, 10.1109/TCS.1977.1084298

Thompson, 1979, Area-time complexity for VLSI

Thompson, 1980, A Complexity Theory for VLSI

Ullman, 1983

Valiant, 1975, On non-linear loweer bounds in computational complexity

Valiant, 1981, Universality considerations in VLSI circuits, IEEE Trans. Comput., 10.1109/TC.1981.6312176