A charge pump with a 0.32 % of current mismatch for a high speed PLL

A charge pump is a widely used circuit in modern PLLs. In order to reduce phase offset, and decrease spurs tones in the PLL output signals, the charge pump current mismatch has to be minimized. In this paper, a charge pump circuit with low current mismatch characteristic that was designed with a standard 0.18 $$\upmu $$ m CMOS technology. A Mentor Graphics environment using Eldo program was used to carry out the schematic, layout, and post-layout simulations. Under 1.8 V DC supply voltage, and 100 $$\upmu $$ A output current, the circuit consumes only 0.56 mW in fully differential mode, and 0.38 mW for a single ended configuration. Using the same bias current for UP, and DN signals, and three wide-swing current mirrors a 0.32 % current mismatch with a 0.3–1.5 V wide output voltage range was achieved. The circuit can be widely used in either single-ended or fully differential phase locked loop structures.