A HW/SW Cross-Layer Approach for Determining Application-Redundant Hardware Faults in Embedded Systems

Christian Bartsch1, Carlos Villarraga1, Dominik Stoffel1, Wolfgang Kunz1
1Department of Electrical and Computer Engineering, University of Kaiserslautern, Kaiserslautern, Germany

Tóm tắt

Từ khóa


Tài liệu tham khảo

Aitch T (2003) Aquarius: a pipelined RISC CPU. http://opencores.org/project,aquarius

Arlat J, Aguera M, Amat L, Crouzet Y, Fabre JC, Laprie JC, Martins E, Powell D (1990) Fault injection for dependability validation: a methodology and some applications. IEEE Trans Softw Eng 16(2):166–182

Bartsch C, Rödel N, Villarraga C, Stoffel DS, Kunz W (2016) A HW-dependent software model for cross-layer fault analysis in embedded systems. In: 17Th latin-american test symposium (LATS), pp 153–158

Bernardeschi C, Fantechi A, Gnesi S (1999) Formal validation of the guards inter-consistency mechanism. In: Computer safety, reliability and security, lecture notes in computer science, vol 1698. Springer, Berlin, pp 420–430

Bernardeschi C, Fantechi A, Gnesi S (2002) Model checking fault tolerant systems. Softw Test Verification Reliab 12(4):251–275

Biere A, Cimatti A, Clarke EM, Fujita M, Zhu Y (1999) Symbolic model checking using SAT procedures instead of BDDs. In: Proc. International design automation conference (DAC), pp 317– 320

Boue J, Petillon P, Crouzet Y (1998) MEFISTO-l: a VHDL-based fault injection tool for the experimental assessment of fault tolerance. In: Digest of papers. Twenty-eighth annual international symposium on fault-tolerant computing, pp 168–173

Clark JA, Pradhan DK (1995) Fault injection: a method for validating computer-system dependability. Computer 28(6):47–56

Cotroneo D, Natella R (2013) Fault injection for software certification. IEEE Secur Priv 11(4):38–45

Darbari A, Hashimi BA, Harrod P, Bradley D (2008) A new approach for transient fault injection using symbolic simulation. In: 14Th IEEE international on-line testing symposium, pp 93– 98

Daveau JM, Blampey A, Gasiot G, Bulone J, Roche P (2009) An industrial fault injection platform for soft-error dependability analysis and hardening of complex system-on-a-chip. In: IEEE International reliability physics symposium, pp 212–220

Ebrahimi M, Chen L, Asadi H, Tahoori MB (2013) CLASS: Combined logic and architectural soft error sensitivity analysis. In: Design automation conference (ASP-DAC), 2013 18th Asia and South Pacific, pp 601–607

Entrena L, Garcia-Valderas M, Fernandez-Cardenal R, Lindoso A, Portela M, Lopez-Ongil C (2012) Soft error sensitivity evaluation of microprocessors by multilevel emulation-based fault injection. IEEE Trans Comput 61(3):313–322

Gracia-Moran J, Baraza-Calvo J, Gil-Tomas D, Saiz-Adalid L, Gil-Vicente P (2014) Effects of intermittent faults on the reliability of a reduced instruction set computing (RISC) microprocessor. IEEE Trans Reliab 63(1):144–153

Grinschgl J, Krieg A, Steger C, Weiss R, Bock H, Haid J (2012) Efficient fault emulation based on post-injection fault effect analysis (pifea). In: IEEE 55Th international midwest symposium on circuits and systems (MWSCAS), pp 526–529

Hari SKS, Venkatagiri R, Adve SV, Naeimi H (2014) GangES: Gang error simulation for hardware resiliency evaluation. In: ACM/IEEE 41St international symposium on computer architecture (ISCA), pp 61–72

Hsueh MC, Tsai T, Iyer R (1997) Fault injection techniques and tools. Computer 30(4):75–82

Kooli M, Natale GD (2014) A survey on simulation-based fault injection tools for complex systems. In: 9Th IEEE international conference on design technology of integrated systems in nanoscale era (DTIS), pp 1–6

Larsson D, Haehnle R (2007) Symbolic fault injection. In: Proceedings 4th international verification workshop (verify) in connection with CADE-21, vol 259, pp 85–103

Li ML, Ramachandran P, Karpuzcu UR, Hari SKS, Adve SV (2009) Accurate microarchitecture-level fault modeling for studying hardware faults. In: IEEE 15Th international symposium on high performance computer architecture, pp 105–116

Li ML, Ramachandran P, Sahoo SK, Adve SV, Adve VS, Zhou Y (2008) Understanding the propagation of hard errors to software and implications for resilient system design. In: Proceedings of the 13th international conference on architectural support for programming languages and operating systems, ASPLOS XIII, pp 265–276

Miele A (2014) A fault-injection methodology for the system-level dependability analysis of multiprocessor embedded systems. Microprocess Microsyst 38(6):567–580

Mukherjee SS, Weaver C, Emer J, Reinhardt SK, Austin T (2003) A systematic methodology to compute the architectural vulnerability factors for a high-performance microprocessor. In: Microarchitecture, 2003. MICRO-36. Proceedings. 36th annual IEEE/ACM international symposium on, pp 29–40

Onespin Solutions GmbH OneSpin 360 DV-Verify. https://www.onespin.com/products/360-dv-verify/

Pattabiraman K, Nakka N, Kalbarczyk Z, Iyer R (2013) Symplfied: Symbolic program-level fault injection and error detection framework. IEEE Trans on Comput 62(11):2292–2307

Perez J, Azkarate-Askasua M, Perez A (2010) Codesign and simulated fault injection of safety-critical embedded systems using systemc. In: European dependable computing conference, pp 221–229

Piper T, Winter S, Suri N, Fuhrman TE (2015) On the effective use of fault injection for the assessment of AUTOSAR safety mechanisms. In: 11Th european dependable computing conference (EDCC), pp 85–96

Portela-Garcia M, Lindoso A, Entrena L, Garcia-Valderas M, Lopez-Ongil C, Marroni N, Pianta B, Poehls LB, Vargas F (2012) Evaluating the effectiveness of a software-based technique under SEEs using FPGA-based fault injection approach. J Electron Test 28(6):777–789

Rashid L, Pattabiraman K, Gopalakrishnan S (2015) Characterizing the impact of intermittent hardware faults on programs. IEEE Trans Reliab 64(1):297–310

Renesas Electronics Corporation TYO (2005) SH-1/SH-2/SH-DSP software manual, rev. 5.0. http://www.renesas.com/

Riefert A, Cantoro R, Sauer M, Reorda MS, Becker B (2016) A flexible framework for the automatic generation of sbst programs. IEEE Trans on Very Large Scale Integr (VLSI) Syst 24(10):3055–3066

Schmidt B, Villarraga C, Fehmel T, Bormann J, Wedler M, Nguyen M, Stoffel D, Kunz W (2013) A new formal verification approach for hardware-dependent embedded system software. IPSJ Trans on Syst LSI Design Methodology (Special Issue on ASPDAC-2013) 6:135–145

Schwarz M, Chaari M, Tabacaru BA, Ecker W (2015) A meta-model-based approach for semantic fault modeling on multiple abstraction levels. In: Design and verification conference and exhibition europe

Sharma A, Sloan J, Wanner L, Elmalaki S, Srivastava M, Gupta P (2013) Towards analyzing and improving robustness of software applications to intermittent and permanent faults in hardware. In: International conference on computer design , pp 435–438

Steiner W, Rushby J, Sorea M, Pfeifer H (2004) Model checking a fault-tolerant startup algorithm: from design exploration to exhaustive fault simulation. In: International conference on dependable systems and networks, pp 189–198

Synopsys Inc. (2010) Design Compiler user guide

Synopsys Inc. (2013) TetraMAX ATPG user guide

Tabacaru BA, Chaari M, Ecker W, Kruse T (2014) A meta-modeling-based approach for automatic generation of fault-injection processes. DVCon Europe pp. 1–7

The SIR Project Software-artifact infrastructure repository. http://sir.unl.edu . Accessed: 2015-09-01

Villarraga C, Schmidt B, Bao B, Raman R, Bartsch C, Fehmel T, Stoffel D, Kunz W (2014) Software in a hardware view: New models for HW-dependent software in SoC verification and test (invited paper). In: Proceedings International test conference (ITC’14)

Villarraga C, Schmidt B, Bartsch C, Bormann J, Stoffel D, Kunz W (2013) An equivalence checker for hardware-dependent software. In: 11. ACM-IEEE International conference on formal methods and models for codesign (MEMOCODE), pp 119–128