A Fully-Integrated 40-Gb/s Transceiver in 65-nm CMOS Technology
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wu, 2003, Differential 4-tap and 7-tap transverse filters in sige for 10 Gb/s multimode fiber optic link equalization, IEEE ISSCC Dig Tech Papers, 180
toifl, 2007, A 72 mW 0.03 mm<formula formulatype="inline"> <tex Notation="TeX">$^{2}$</tex></formula> inductorless 40 Gb/s CDR in 65 nm SOI CMOS, IEEE ISSCC Dig Tech Papers, 226
lee, 2003, A 40-Gb/s clock and data recovery circuit in 0.18-<formula formulatype="inline"><tex Notation="TeX">$\mu{\hbox{m}}$</tex> </formula> CMOS technology, IEEE J Solid-State Circuits, 38, 2181, 10.1109/JSSC.2003.818566
wu, 2010, A <formula formulatype="inline"><tex Notation="TeX">$2\times 25$</tex></formula>-Gb/s receiver with 2:5 DMUX for 100-Gb/s Ethernet, IEEE J Solid-State Circuits, 45, 2421
0, Rogers Corporation
wang, 2009, A 40-Gb/s transmitter with 4:1 MUX and subharmonically injection-locked CMU in 90-nm CMOS technology, Symp VLSI Circuits Dig Tech Papers, 48
casper, 2006, A 20 Gb/s forwarded clock transceiver in 90 nm CMOS, IEEE ISSCC Dig Tech Papers, 90
nowell, 2007, Overview of Requirements and Applications for 40 Gigabit and 100 Gigabit Ethernet
0, Astro Advanced Physical Optimization Placement and Routing Solution for System-on-Chip Designs
0, DFT Compiler Standard Scan Synthesis