A Chip for Linearization of RF Power Amplifiers using Predistortion based on a Bit-Parallel Complex Multiplier
Tóm tắt
This paper presents a custom chip for linearization of RF power amplifiers using digital predistortion. The chip has been implemented in a standard digital 0.8 μm CMOS process with standard static cells and single-phase clocking. A systolic complex multiplier based on distributed arithmetic constitutes the core of the chip. The nonlinear function is realized with a look-up table containing complex gain factors applied to the complex multiplier. Maximum clock frequency was found by means of simulation to be 105 MHz corresponding to 21 Msamples/s throughput with 3 W power consumption using 5 V supply voltage. The fabricated chip is fully functional and has been measured up to 60 MHz clock frequency with 825 mW power consumption with 3.3 V supply voltage. Operation at 1.5 V supply voltage allows 10 MHz clock frequency with 35 mW power consumption.
Tài liệu tham khảo
J. K. Cavers, “A linearising predistorter with fast adaptation,” in Proceedings of IEEE 40th Vehicular Technology Conference, pp. 41–47, 1990.
L. Sundström, M. Faulkner, and M. Johansson, “Quantization analysis and design of a digital predistortion linearizer for RF power amplifiers.” IEEE Transactions on Vehicular Technology VT-45, pp. 707–719, 1996.
L. Sundström, M. Faulkner, and M. Johansson, “Effects of reconstruction filter in digital predistortion linearizers for RF power amplifiers.” IEEE Transactions on Vehicular Technology VT-44, pp. 131–139, 1995.
L. Sundström, “Chip for linearization of RF power amplifiers using digital predistortion.” Electronics Letters 30(14), pp. 1123–1124, 1994.
P. Andreani and L. Sundströ m, “Chip for wideband digital predistortion RF power amplifier linearization.” Electronics Letters 33(11), pp. 925–926, 1997.
S. He and M. Torkelson, “A Complex Array Multiplier Using Distributed Arithmetic.” In Proceedings of IEEE CICC'96, pp. 71–74, May 1996.