A 700 V narrow channel nJFET with low pinch-off voltage and suppressed drain-induced barrier lowering effect

Superlattices and Microstructures - Tập 75 - Trang 576-585 - 2014
Kun Mao1, Ming Qiao1, WenTong Zhang1, Bo Zhang1, Zhaoji Li1
1State Key Laboratory of Electronic Thin Films and Integrated Devices, University of Electronic Science & Technology of China, Chengdu, China

Tài liệu tham khảo

Li, 2007, Analysis and performance of a smart, high-voltage SenseFET, Chin. J. Semicond., 28, 1961 Hung, 2010, High voltage JFET with adjustable pinch-off voltage, ICSICT, 963 Chen, 2006, A novel double RESURF LDMOS and a versatile JFET device used as internal power supply and current detector for SPIC, Microelectron. J., 37, 574, 10.1016/j.mejo.2005.09.017 Orouji, 2012, Novel partially depleted SOI MOSFET for suppression floating-body effect: an embedded JFET structure, Superlattices Microstruct., 52, 552, 10.1016/j.spmi.2012.06.006 Treu, 2006, Commercial SiC device processing: status and requirements with respect to SiC based power devices, Superlattices Microstruct., 40, 380, 10.1016/j.spmi.2006.09.005 Hu, 2012, A novel high voltage start-up current source for SMPS, IEEE ISPSD, 197 Hu, 2014, Thin silicon layer p-channel SOI/PSOI LDMOS with interface n+-islands for high voltage application, Superlattices Microstruct., 67, 1, 10.1016/j.spmi.2013.11.027 Yuzhan, 2009, Annealing behavior of radiation damage in JFET-input operational amplifiers, J. Semicond., 30, 055001, 10.1088/1674-4926/30/5/055001 Pressman, 1998 Ming, 2012, A 700V BCD technology platform for high voltage applications, J. Semicond., 33, 044004, 10.1088/1674-4926/33/4/044004 Li, 2011, A controllable high-voltage C-SenseFET by inserting the second gate, IEEE Trans. Power Electron., 26, 10.1109/TPEL.2010.2093152 Mao, 2013, A low-cost low-power HV startup circuit with 50V pJFET and 700V T-nJFET, Electron. Lett., 49, 1318, 10.1049/el.2013.2459 Hao, 2013, Versatile HV lateral JFETs design in a 0.18μm SOI superjunction BCD technology, IEEE ISPSD, 143 Mao, 2013, A 0.35μm 700V BCD technology with self-isolated and non-isolated ultra-low specific on-resistance DB-nLDMOS, IEEE ISPSD, 397 Peng, 2004, A passive soft switching snubber for PWM inverters, IEEE Trans. Power Electron., 19, 363, 10.1109/TPEL.2003.823204 Yamaguchi, 1977, Optimum design of triode-like JFET’s by two-dimensional computer simulation, IEEE Trans. Electron Devices, ED-24, 10.1109/T-ED.1977.18877