A 56-Gb/s PAM4 Receiver With Low-Overhead Techniques for Threshold and Edge-Based DFE FIR- and IIR-Tap Adaptation in 65-nm CMOS

10.1109/JSSC.2017.2705070

tang, 2018, A 32 Gb/s 133 mW PAM-4 transceiver with DFE based on adaptive clock phase and threshold voltage in 65 nm CMOS, IEEE ISSCC Dig Tech Papers, 114

10.1109/CICC.2018.8357009

shahramian, 2016, A 16 Gb/s 1 IIR + 1 DT DFE compensating 28 dB loss with edge-based adaptation converging in $5~\mu$ s, IEEE ISSCC Dig Tech Papers, 410

roshan-zamir, 2016, A 16/32 Gb/s dual-mode NRZ/PAM4 SerDes in 65 nm CMOS, Proc IEEE Compound Semiconductor Integr Circuit Symp (CSICS), 1

10.1109/JSSC.1996.542315

10.1109/JSSC.2009.2036761

10.1109/4.509864

10.1109/JSSC.2013.2278804

10.1109/ASSCC.2017.8240223

10.1109/CICC.2018.8357008

10.1109/ISSCC.2018.8310207

10.1109/JSSC.2017.2749432

10.1109/JSSC.2016.2632300

10.1109/VLSIC.2015.7231265

10.1109/ISSCC.2017.7870285

2016, IEEE P802 3bs 200 Gb/s and 400 Gb/s Ethernet Task Force

2016, CEI-56G-VSR_PAM4 Very Short Reach Interface

10.1109/JSSC.2015.2402218

10.1109/JSSC.2003.818566

10.1109/4.972142