A 22 to 26.5 Gb/s Optical Receiver With All-Digital Clock and Data Recovery in a 65 nm CMOS Process
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andreani, 2002, A 2 GHz, 17% tuning range quadrature CMOS VCO with high figure-of-merit and 0.6<formula formulatype="inline"><tex Notation="TeX">$^{\circ}$</tex></formula> phase error, Proc ESSCIRC, 815
huang, 2014, A 28 Gb/s 1 pJ/b shared-inductor optical receiver with 56% chip-area reduction in 28 nm CMOS, IEEE ISSCC Dig Tech Papers, 144
proesel, 2012, 25 Gb/s 3.6 pJ/b and 15 Gb/s 1.37 pJ/b VCSEL-based optical links in 90 nm CMOS, IEEE ISSCC Dig Tech Papers, 418
da dalt, 2006, A 10 b 10 GHz digitlly controlled LC oscillator in 65 nm CMOS, IEEE ISSCC Dig Tech Papers, 669
oh, 2007, A 2.8 Gb/s all-digital CDR with a 10 b monotonic DCO, IEEE ISSCC Dig Tech Papers, 222
chu, 2014, A 26.5 Gb/s optical receiver with all-digital clock and data recovery in 65 nm CMOS process, Proc IEEEI SSCC Dig, 101
2002, ?HFAN-09 0 1 NRZ Bandwidth-HF Cutoff vs SNR ?
walker, 2003, Phase-Locking in High Performance Systems, 34
toifl, 2012, A 3.1 mW/Gbps 30 Gbps quarter-rate triple-speculation 15-tap SC-DFE RX data path in 32 nm CMOS, IEEE Symp VLSI Circuits Dig, 102
2010, Standard
frans, 2004, A 1?4 Gbps quad transceiver cell using PLL with gate-current leakage compensator in 90 nm CMOS, IEEE Symp VLSI Circuits Dig, 134
jeong, 2014, A 20-Gb/s 1.27 pJ/b low-power optical receiver front-end in 65 nm CMOS, Proc IEEE ISCAS, 1492
saleh, 2007, Fundamentals of Photonics
rylyakov, 2015, A 25 Gb/s burst-mode receiver for rapidly reconfigurable optical networks, IEEE ISSCC Dig Tech Papers, 400