A 22 to 26.5 Gb/s Optical Receiver With All-Digital Clock and Data Recovery in a 65 nm CMOS Process

Institute of Electrical and Electronics Engineers (IEEE) - Tập 50 Số 11 - Trang 2603-2612 - 2015
Sang-Hyeok Chu, Woorham Bae, Gyu-Seob Jeong, Sungchun Jang, Sung Woo Kim, Jiho Joo, Gyungock Kim, Deog‐Kyoon Jeong

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10.1109/JSSC.2011.2168869

10.1109/JSSC.2014.2365700

andreani, 2002, A 2 GHz, 17% tuning range quadrature CMOS VCO with high figure-of-merit and 0.6<formula formulatype="inline"><tex Notation="TeX">$^{\circ}$</tex></formula> phase error, Proc ESSCIRC, 815

10.1109/JSSC.2002.804352

10.1109/JSSC.2003.813218

10.1109/ISSCC.1996.488731

10.1109/JSSC.2014.2349976

huang, 2014, A 28 Gb/s 1 pJ/b shared-inductor optical receiver with 56% chip-area reduction in 28 nm CMOS, IEEE ISSCC Dig Tech Papers, 144

proesel, 2012, 25 Gb/s 3.6 pJ/b and 15 Gb/s 1.37 pJ/b VCSEL-based optical links in 90 nm CMOS, IEEE ISSCC Dig Tech Papers, 418

da dalt, 2006, A 10 b 10 GHz digitlly controlled LC oscillator in 65 nm CMOS, IEEE ISSCC Dig Tech Papers, 669

10.1109/CICC.2007.4405753

10.1109/JSSC.2014.2369494

10.1109/JSSC.2010.2082272

10.1109/JSSC.2004.836345

oh, 2007, A 2.8 Gb/s all-digital CDR with a 10 b monotonic DCO, IEEE ISSCC Dig Tech Papers, 222

chu, 2014, A 26.5 Gb/s optical receiver with all-digital clock and data recovery in 65 nm CMOS process, Proc IEEEI SSCC Dig, 101

10.1109/JSSC.2011.2178723

10.1109/JRPROC.1944.232049

2002, ?HFAN-09 0 1 NRZ Bandwidth-HF Cutoff vs SNR ?

10.1109/ECCTD.2009.5275025

walker, 2003, Phase-Locking in High Performance Systems, 34

10.1049/piee.1963.0050

toifl, 2012, A 3.1 mW/Gbps 30 Gbps quarter-rate triple-speculation 15-tap SC-DFE RX data path in 32 nm CMOS, IEEE Symp VLSI Circuits Dig, 102

10.1109/JSSC.2003.818567

10.1109/JSSC.2009.2034444

2010, Standard

10.1109/4.494195

10.1109/JSSC.2012.2216414

10.1109/JSSC.2011.2157254

10.1109/MSSC.2012.2232791

10.1109/5.867687

frans, 2004, A 1?4 Gbps quad transceiver cell using PLL with gate-current leakage compensator in 90 nm CMOS, IEEE Symp VLSI Circuits Dig, 134

10.1109/PROC.1984.12943

10.1109/JSSC.2009.2017973

10.1109/JSSC.2014.2322868

10.1109/JSSC.2004.827807

10.1109/RFIC.2014.6851720

jeong, 2014, A 20-Gb/s 1.27 pJ/b low-power optical receiver front-end in 65 nm CMOS, Proc IEEE ISCAS, 1492

10.1364/OFC.2013.OM2H.2

saleh, 2007, Fundamentals of Photonics

10.1109/TCSII.2004.836883

rylyakov, 2015, A 25 Gb/s burst-mode receiver for rapidly reconfigurable optical networks, IEEE ISSCC Dig Tech Papers, 400

10.1109/4.826816